Abstract: The present invention provides a semiconductor device relaxing the electric field concentration in a gate insulating film just below a gate electrode, and a production method therefor. The semiconductor device has a third semiconductor layer, a gate insulating film, a gate electrode, and a passivation film. The gate insulating film has a gate electrode contact region being in contact with the gate electrode, and a gate electrode non-contact region not being in contact with the gate electrode. The passivation film has a dielectric constant higher than the dielectric constant of the gate insulating film. A thickness of the gate electrode contact region and a thickness of the gate electrode non-contact region satisfy the following equation 0.8?t2/t1<1.

Abstract: The present invention provides a semiconductor device relaxing the electric field concentration in a gate insulating film just below a gate electrode, and a production method therefor. The semiconductor device has a third semiconductor layer, a gate insulating film, a gate electrode, and a passivation film. The gate insulating film has a gate electrode contact region being in contact with the gate electrode, and a gate electrode non-contact region not being in contact with the gate electrode. The passivation film has a dielectric constant higher than the dielectric constant of the gate insulating film. A thickness of the gate electrode contact region and a thickness of the gate electrode non-contact region satisfy the following equation 0.8?t2/t1<1.

Abstract: In an image forming apparatus, a cleaning member is pressed against a circumferential surface of an image bearing member and collects a toner remaining on the circumferential surface of the image bearing member. The toner has a number average roundness of 0.965 to 0.998. The toner has a D50 of 4.0 ?m to 7.0 ?m. A linear pressure of the cleaning member on the circumferential surface of the image bearing member is 10 N/m to 40 N/m. The image bearing member includes a single-layer photosensitive layer containing a charge generating material and a hole transport material. Ionization potential IpHTM of the hole transport material and ionization potential IpCGM of the charge generating material satisfy mathematical formula (1) “IpHTM?5.30 eV”, mathematical formula (2) “IpCGM?5.30 eV”, and mathematical formula (3) “0.09 eV?|IpHTM?IpCGM|?0.30 eV”.

Abstract: A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity. In the ion implantation process, at least one of the n-type impurity and the p-type impurity is ion-implanted into the p-type semiconductor layer located in the edge termination region. The ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a p-type impurity containing region in at least part of the n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.

Abstract: To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region.

Abstract: An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.

Abstract: Provided is a formed body in which a first region and a second region having gloss values different from each other are formed, and at least any one of the first region and the second region is a region to which an inkjet ink is applied.

Abstract: An image forming apparatus includes an image bearing member and a static elimination device. The static elimination device irradiates static elimination light onto a circumferential surface of the image bearing member. The image bearing member includes a conductive substrate and a single-layer photosensitive layer. The photosensitive layer contains a charge generating material, a hole transport material, an electron transport material, and a binder resin. The static elimination light has a wavelength of at least 600 nm and no greater than 800 nm. The photosensitive layer has an optical absorption coefficient of at least 600 cm?1 and no greater than 1,500 cm?1 with respect to light having a wavelength of 660 nm.

Abstract: An image forming apparatus includes an image bearing member, a charger, and a cleaning member. The charger charges a circumferential surface of the image bearing member to a positive polarity. The cleaning member is pressed against the circumferential surface of the image bearing member and collects a toner remaining on the circumferential surface of the image bearing member. A linear pressure N of the cleaning member on the circumferential surface of the image bearing member is at least 14 N/m and no greater than 40 N/m. A rebound resilience R of the cleaning member at a temperature of 25° C. is at least 38%. The leaner pressure N and the rebound resilience R satisfy mathematical formula (1A). The image bearing member satisfies mathematical formula (1B). R < 13.771 × N 0.4043 ( 1 ? A ) 0.

Abstract: An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.

Abstract: An image forming apparatus includes an image bearing member, a charger, and a cleaning member. The charger charges a circumferential surface of the image bearing member to a positive polarity. The cleaning member is pressed against the circumferential surface of the image bearing member and collects a toner remaining on the circumferential surface of the image bearing member. A linear pressure of the cleaning member on the circumferential surface of the image bearing member is at least 10 N/m and no greater than 40 N/m. The image bearing member includes a conductive substrate and a single-layer photosensitive layer. The single-layer photosensitive layer contains a charge generating material, a hole transport material, an electron transport material, and a binder resin. The image bearing member satisfies formula (1) 0.60 ? V ( Q / S ) × ( d / ? r · ? 0 ) .

Abstract: An image forming apparatus includes an image bearing member and a static elimination device. The static elimination device irradiates static elimination light onto a circumferential surface of the image bearing member. The image bearing member includes a conductive substrate and a single-layer photosensitive layer. The photosensitive layer contains a charge generating material, a hole transport material, an electron transport material, and a binder resin. The static elimination light has a wavelength of at least 600 nm and no greater than 800 nm. The photosensitive layer has an optical absorption coefficient of at least 600 cm?1 and no greater than 1,500 cm?1 with respect to light having a wavelength of 660 nm.

Abstract: In an image forming apparatus, a cleaning member is pressed against a circumferential surface of an image bearing member and collects a toner remaining on the circumferential surface of the image bearing member. The toner has a number average roundness of 0.965 to 0.998. The toner has a D50 of 4.0 ?m to 7.0 ?m. A linear pressure of the cleaning member on the circumferential surface of the image bearing member is 10 N/m to 40 N/m. The image bearing member includes a single-layer photosensitive layer containing a charge generating material and a hole transport material. Ionization potential IpHTM of the hole transport material and ionization potential IpCGM of the charge generating material satisfy mathematical formula (1) “IpHTM?5.30 eV”, mathematical formula (2) “IpCGM?5.30 eV”, and mathematical formula (3) “0.09 eV?|IpHTM?IpCGM|?0.30 eV”.

Abstract: An image forming apparatus includes an image bearing member, a charger, and a cleaning member. The charger charges a circumferential surface of the image bearing member to a positive polarity. The cleaning member is pressed against the circumferential surface of the image bearing member and collects a toner remaining on the circumferential surface of the image bearing member. A linear pressure N of the cleaning member on the circumferential surface of the image bearing member is at least 14 N/m and no greater than 40 N/m. A rebound resilience R of the cleaning member at a temperature of 25° C. is at least 38%. The leaner pressure N and the rebound resilience R satisfy mathematical formula (1A). The image bearing member satisfies mathematical formula (1B) R < 13.771 × N 0.4043 ( 1 ? A ) 0.

Abstract: A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of Group III nitride containing a p-type impurity on a first n-type semiconductor layer of Group III nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.

Abstract: To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region.

Abstract: In an image forming apparatus, a resistance component of an inner impedance of an electricity removing member is equal to or lower than a value that is obtained by multiplying a calculated resistance value by a first specific value, the calculated resistance value being calculated based on a predetermined formula as a DC resistance value of the electricity removing member that is required to reduce a pre-electricity-removal potential of a photoconductor to a predetermined post-electricity-removal potential during an electricity removal time, the first specific value being calculated based on a ratio of a linear speed of the electricity removing member to a linear speed of the photoconductor, and a resistance component of the contact impedance of the electricity removing member is equal to or lower than a value that is obtained by multiplying the calculated resistance value by a second specific value that is calculated based on the ratio.

Abstract: A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm?2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm?2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer.

Abstract: In an image forming apparatus, a resistance component of an inner impedance of an electricity removing member is equal to or lower than a value that is obtained by multiplying a calculated resistance value by a first specific value, the calculated resistance value being calculated based on a predetermined formula as a DC resistance value of the electricity removing member that is required to reduce a pre-electricity-removal potential of a photoconductor to a predetermined post-electricity-removal potential during an electricity removal time, the first specific value being calculated based on a ratio of a linear speed of the electricity removing member to a linear speed of the photoconductor, and a resistance component of the contact impedance of the electricity removing member is equal to or lower than a value that is obtained by multiplying the calculated resistance value by a second specific value that is calculated based on the ratio.

Abstract: A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.