Abstract: A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.

Abstract: A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type impurity is provided. A method of manufacturing a semiconductor device having a trench gate structure comprises an n-type semiconductor region forming process. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which a p-type impurity contained in a p-type semiconductor layer is diffused is formed in at least part of an n-type semiconductor layer that is located below an n-type semiconductor region.

Abstract: A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of a nitride semiconductor containing gallium; a p-type semiconductor region arranged to be adjacent to and in contact with the n-type semiconductor region and made of the nitride semiconductor; a first electrode arranged to be in ohmic contact with the n-type semiconductor region; and a second electrode arranged to be in ohmic contact with the p-type semiconductor region. The first electrode and the second electrode are mainly made of one identical metal. The identical metal is at least one metal selected from the group consisting of palladium, nickel and platinum. A concentration of a p-type impurity in the n-type semiconductor region is approximately equal to a concentration of the p-type impurity in the p-type semiconductor region.

Abstract: A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity. In the ion implantation process, at least one of the n-type impurity and the p-type impurity is ion-implanted into the p-type semiconductor layer located in the edge termination region. The ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a p-type impurity containing region in at least part of the n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.

Abstract: A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of Group III nitride containing a p-type impurity on a first n-type semiconductor layer of Group III nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.

Abstract: A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.

Abstract: An image forming apparatus includes a photoconductor and an electricity removing member electrically grounded and disposed to be in contact with a surface of the photoconductor. In the image forming apparatus, with regard to a capacitance component of an inner impedance of the electricity removing member and a capacitance component of a contact impedance of the electricity removing member that are calculated from a Cole-Cole plot obtained from measurement by an AC impedance method in a predetermined frequency range, a value obtained by dividing the capacitance component of the contact impedance by the capacitance component of the inner impedance is equal to or lower than a predetermined first specific value, and the capacitance component of the inner impedance is equal to or lower than a predetermined second specific value.

Abstract: A semiconductor device includes a substrate, a semiconductor layer that is formed on the substrate and includes a pn junction or a hetero-junction, an insulating film that is formed on the semiconductor layer to be in contact with an end of the pn junction or an end of the hetero-junction, and an electrode formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

Abstract: To improve the breakdown voltage of a semiconductor device. In a terminal region of the semiconductor device, a mesa groove, a recess groove, an electric field relaxation region, and a gradient distributed low concentration p-type layer region are formed. A recess groove is fromed between a device region and the mesa groove so as to surround the device region. A region where a p-type layer is thinned by the recess groove is the electric field relaxation region. The gradient distributed low concentration p-type layer region is formed on the surface of the electric field relaxation region. The average carrier concentration of the entire gradient distributed low concentration p-type layer region is lower than the carrier concentration of the p-type layer. By forming the gradient distributed low concentration p-type layer region, the electric field relaxation region is quickly completely depleted when a reverse voltage is applied, thereby improving the breakdown voltage.

Abstract: There is provided a semiconductor device configured to include a plurality of semiconductor units formed in a semiconductor layer. Each of the semiconductor units comprises a mesa portion; a Schottky electrode formed on the mesa portion; an insulating film formed continuously on another portion of the Schottky electrode that is nearer to an edge of an upper face of the mesa portion than one portion of the Schottky electrode, on a side face of the mesa portion, and on a surface of the semiconductor layer other than the mesa portion; and a wiring electrode formed on the Schottky electrode and the insulating film. An angle between the side face of the mesa portion and the surface of the semiconductor layer is 90 degrees. A part of the wiring electrode is placed between the insulating films formed on opposed side faces of adjacent mesa portions.

Abstract: There is provided a semiconductor device configured to include a plurality of semiconductor units formed in a semiconductor layer. Each of the semiconductor units comprises a mesa portion; a Schottky electrode formed on the mesa portion; an insulating film formed continuously on another portion of the Schottky electrode that is nearer to an edge of an upper face of the mesa portion than one portion of the Schottky electrode, on a side face of the mesa portion, and on a surface of the semiconductor layer other than the mesa portion; and a wiring electrode formed on the Schottky electrode and the insulating film. An angle between the side face of the mesa portion and the surface of the semiconductor layer is 90 degrees. A part of the wiring electrode is placed between the insulating films formed on opposed side faces of adjacent mesa portions.

Abstract: To improve the breakdown voltage of a semiconductor device. In a terminal region of the semiconductor device, a mesa groove, a recess groove, an electric field relaxation region, and a gradient distributed low concentration p-type layer region are formed. A recess groove is fromed between a device region and the mesa groove so as to surround the device region. A region where a p-type layer is thinned by the recess groove is the electric field relaxation region. The gradient distributed low concentration p-type layer region is formed on the surface of the electric field relaxation region. The average carrier concentration of the entire gradient distributed low concentration p-type layer region is lower than the carrier concentration of the p-type layer. By forming the gradient distributed low concentration p-type layer region, the electric field relaxation region is quickly completely depleted when a reverse voltage is applied, thereby improving the breakdown voltage.

Abstract: An image forming apparatus includes a photoconductor and an electricity removing member electrically grounded and disposed to be in contact with a surface of the photoconductor. In the image forming apparatus, with regard to a capacitance component of an inner impedance of the electricity removing member and a capacitance component of a contact impedance of the electricity removing member that are calculated from a Cole-Cole plot obtained from measurement by an AC impedance method in a predetermined frequency range, a value obtained by dividing the capacitance component of the contact impedance by the capacitance component of the inner impedance is equal to or lower than a predetermined first specific value, and the capacitance component of the inner impedance is equal to or lower than a predetermined second specific value.

Abstract: A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm?2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm?2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer.

Abstract: A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type impurity is provided. A method of manufacturing a semiconductor device having a trench gate structure comprises an n-type semiconductor region forming process. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which a p-type impurity contained in a p-type semiconductor layer is diffused is formed in at least part of an n-type semiconductor layer that is located below an n-type semiconductor region.

Abstract: A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of a nitride semiconductor containing gallium; a p-type semiconductor region arranged to be adjacent to and in contact with the n-type semiconductor region and made of the nitride semiconductor; a first electrode arranged to be in ohmic contact with the n-type semiconductor region; and a second electrode arranged to be in ohmic contact with the p-type semiconductor region. The first electrode and the second electrode are mainly made of one identical metal. The identical metal is at least one metal selected from the group consisting of palladium, nickel and platinum. A concentration of a p-type impurity in the n-type semiconductor region is approximately equal to a concentration of the p-type impurity in the p-type semiconductor region.

Abstract: A semiconductor device includes a substrate, a semiconductor layer that is formed on the substrate and includes a pn junction or a hetero-junction, an insulating film that is formed on the semiconductor layer to be in contact with an end of the pn junction or an end of the hetero-junction, and an electrode formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

Abstract: A technique of suppressing leak current in a semiconductor device is provided. A semiconductor device, comprises: a semiconductor layer made of a semiconductor; an insulating layer configured to have electric insulation property and formed to cover part of the semiconductor layer; a first electrode layer formed on the semiconductor layer, configured to have a work function of not less than 0.5 eV relative to electron affinity of the semiconductor layer and extended to surface of the insulating layer to form a field plate structure; and a second electrode layer configured to have electrical conductivity and formed to cover at least part of the first electrode layer. A distance between an edge of a part of the first electrode layer that is in contact with the semiconductor layer and the second electrode layer is equal to or greater than 0.2 ?m.

Abstract: A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

Abstract: An object is to avoid an increase in contact resistance of an ohmic electrode by etching in a semiconductor device. There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises forming a semiconductor layer; forming an ohmic electrode by stacking a plurality of metal layers, on the semiconductor layer; forming another metal layer that is mainly made of another metal different from a material of an outermost layer among the plurality of metal layers, on the ohmic electrode; removing the another metal layer from top of the ohmic electrode by etching; and processing the ohmic electrode by heat treatment, subsequent to the etching.