Patents by Inventor Nariaki Tanaka

Nariaki Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9653564
    Abstract: There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises a film formation process of forming a molybdenum layer that is mainly made of molybdenum (Mo), on at least one of a semiconductor layer, an insulating film and an electrode in the semiconductor device; a heat treatment process of heating the molybdenum layer at temperature of not lower than 200° C.; and a dry etching process of processing the semiconductor device that includes the formed molybdenum layer by dry etching, subsequent to the heat treatment process.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 16, 2017
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nariaki Tanaka, Tohru Oka
  • Patent number: 9583580
    Abstract: A manufacturing method of a semiconductor device, includes: a stacking process of forming an electrode by stacking a plurality of electrode layers on a semiconductor layer; and a anneal treatment process of treating the electrode. The stacking process including processes of forming a first electrode layer mainly made of aluminum (Al) as one of the plurality of electrode layers; forming a second electrode layer mainly made of a conductive material that has a higher melting point than that of aluminum (Al) and reacts with aluminum (Al) at 450° C. or higher temperature, as one of the plurality of electrode layers, on the first electrode layer; and forming a third electrode layer mainly made of palladium (Pd) as an electrode layer most distant from the semiconductor layer among the plurality of electrode layers, on the second electrode layer.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 28, 2017
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nariaki Tanaka, Tohru Oka
  • Patent number: 9559218
    Abstract: A semiconductor device comprises a semiconductor layer including a mesa structure and a peripheral surface extending around the mesa structure, the mesa structure having a plateau shape with an upper surface and a side surface; a Schottky electrode forming a Schottky junction with the upper surface; an insulating film extending from the peripheral surface, across the side surface, and onto the Schottky electrode, the insulating film having an opening formed on the Schottky electrode; and a wiring electrode electrically connected to the Schottky electrode inside the opening, the wiring electrode extending from inside of the opening, across a portion of the insulating film formed on the side surface, and onto another portion of the insulating film formed on the peripheral surface.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: January 31, 2017
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Kazuya Hasegawa, Tohru Oka, Nariaki Tanaka
  • Publication number: 20160365421
    Abstract: A technique of improving the barrier height between an electrode layer and a semiconductor layer is provided. A semiconductor device comprises a semiconductor layer made of a semiconductor and an electrode layer formed to be at least partly in Schottky contact with the semiconductor layer. The electrode layer includes a first layer and a second layer arranged sequentially from a semiconductor layer-side. The first layer is a layer mainly made of nickel and has a film thickness of not less than 50 nm and not greater than 200 nm. The second layer is a layer mainly made of at least one metal selected from the group consisting of palladium, platinum and iridium. The second layer has a film thickness that is equal to or greater than the film thickness of the first layer.
    Type: Application
    Filed: January 31, 2015
    Publication date: December 15, 2016
    Inventors: Kazuya HASEGAWA, Tohru Oka, Nariaki Tanaka
  • Publication number: 20160284812
    Abstract: There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises a film formation process of forming a molybdenum layer that is mainly made of molybdenum (Mo), on at least one of a semiconductor layer, an insulating film and an electrode in the semiconductor device; a heat treatment process of heating the molybdenum layer at temperature of not lower than 200° C.; and a dry etching process of processing the semiconductor device that includes the formed molybdenum layer by dry etching, subsequent to the heat treatment process.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 29, 2016
    Inventors: Nariaki TANAKA, Tohru OKA
  • Publication number: 20160276172
    Abstract: An object is to avoid an increase in contact resistance of an ohmic electrode by etching in a semiconductor device. There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises forming a semiconductor layer; forming an ohmic electrode by stacking a plurality of metal layers, on the semiconductor layer; forming another metal layer that is mainly made of another metal different from a material of an outermost layer among the plurality of metal layers, on the ohmic electrode; removing the another metal layer from top of the ohmic electrode by etching; and processing the ohmic electrode by heat treatment, subsequent to the etching.
    Type: Application
    Filed: February 26, 2016
    Publication date: September 22, 2016
    Inventors: Tsutomu INA, Tohru OKA, Nariaki TANAKA
  • Patent number: 9443950
    Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 13, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, Nariaki Tanaka
  • Publication number: 20160254392
    Abstract: A semiconductor device comprises a semiconductor layer including a mesa structure and a peripheral surface extending around the mesa structure, the mesa structure having a plateau shape with an upper surface and a side surface; a Schottky electrode forming a Schottky junction with the upper surface; an insulating film extending from the peripheral surface, across the side surface, and onto the Schottky electrode, the insulating film having an opening formed on the Schottky electrode; and a wiring electrode electrically connected to the Schottky electrode inside the opening, the wiring electrode extending from inside of the opening, across a portion of the insulating film formed on the side surface, and onto another portion of the insulating film formed on the peripheral surface.
    Type: Application
    Filed: February 18, 2016
    Publication date: September 1, 2016
    Inventors: Kazuya Hasegawa, Tohru Oka, Nariaki Tanaka
  • Patent number: 9431260
    Abstract: There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing method comprises: a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction and make the plane in the thickness direction of the P-type semiconductor layer exposed; and a annealing process of annealing the P-type semiconductor layer in an atmosphere containing oxygen, after the dry etching process. This manufacturing method improves the electrical properties of the P-type semiconductor layer.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: August 30, 2016
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Nariaki Tanaka, Tohru Oka
  • Patent number: 9391150
    Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer; a first electrode layer; a second electrode layer; and a control electrode layer. The first and second electrode layers are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. The second electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, and is formed to be extended to a position on a control electrode layer side of the connection line.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: July 12, 2016
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toru Oka, Nariaki Tanaka
  • Publication number: 20160163792
    Abstract: A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 9, 2016
    Inventors: Tohru OKA, Kazuya HASEGAWA, Noriaki MURAKAMI, Takahiro SONOYAMA, Nariaki TANAKA
  • Patent number: 9331157
    Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, with a surface of the p-type semiconductor layer and with at least a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: May 3, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, Nariaki Tanaka
  • Publication number: 20160087051
    Abstract: A manufacturing method of a semiconductor device, includes: a stacking process of forming an electrode by stacking a plurality of electrode layers on a semiconductor layer; and a anneal treatment process of treating the electrode. The stacking process including processes of forming a first electrode layer mainly made of aluminum (Al) as one of the plurality of electrode layers; forming a second electrode layer mainly made of a conductive material that has a higher melting point than that of aluminum (Al) and reacts with aluminum (Al) at 450° C. or higher temperature, as one of the plurality of electrode layers, on the first electrode layer; and forming a third electrode layer mainly made of palladium (Pd) as an electrode layer most distant from the semiconductor layer among the plurality of electrode layers, on the second electrode layer.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 24, 2016
    Inventors: Nariaki Tanaka, Tohru Oka
  • Publication number: 20150295096
    Abstract: A technique of suppressing leak current in a semiconductor device is provided. A semiconductor device, comprises: a semiconductor layer made of a semiconductor; an insulating layer configured to have electric insulation property and formed to cover part of the semiconductor layer; a first electrode layer formed on the semiconductor layer, configured to have a work function of not less than 0.5 eV relative to electron affinity of the semiconductor layer and extended to surface of the insulating layer to form a field plate structure; and a second electrode layer configured to have electrical conductivity and formed to cover at least part of the first electrode layer. A distance between an edge of a part of the first electrode layer that is in contact with the semiconductor layer and the second electrode layer is equal to or greater than 0.2 ?m.
    Type: Application
    Filed: February 2, 2015
    Publication date: October 15, 2015
    Inventors: Tohru OKA, Kazuya HASEGAWA, Nariaki TANAKA, Noriaki MURAKAMI
  • Patent number: 9123635
    Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 1, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, Nariaki Tanaka
  • Publication number: 20150162208
    Abstract: There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing method comprises: a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction and make the plane in the thickness direction of the P-type semiconductor layer exposed; and a annealing process of annealing the P-type semiconductor layer in an atmosphere containing oxygen, after the dry etching process. This manufacturing method improves the electrical properties of the P-type semiconductor layer.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 11, 2015
    Inventors: Nariaki TANAKA, Tohru Oka
  • Publication number: 20140167062
    Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, NARIAKI TANAKA
  • Publication number: 20140167061
    Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, Nariaki Tanaka
  • Publication number: 20140167147
    Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, with a surface of the p-type semiconductor layer and with at least a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, Nariaki Tanaka
  • Publication number: 20140167148
    Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer; a first electrode layer; a second electrode layer; and a control electrode layer. The first and second electrode layers are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. The second electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, and is formed to be extended to a position on a control electrode layer side of the connection line.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, Nariaki Tanaka