Patents by Inventor Nariaki Tanaka
Nariaki Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9653564Abstract: There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises a film formation process of forming a molybdenum layer that is mainly made of molybdenum (Mo), on at least one of a semiconductor layer, an insulating film and an electrode in the semiconductor device; a heat treatment process of heating the molybdenum layer at temperature of not lower than 200° C.; and a dry etching process of processing the semiconductor device that includes the formed molybdenum layer by dry etching, subsequent to the heat treatment process.Type: GrantFiled: March 7, 2016Date of Patent: May 16, 2017Assignee: TOYODA GOSEI CO., LTD.Inventors: Nariaki Tanaka, Tohru Oka
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Patent number: 9583580Abstract: A manufacturing method of a semiconductor device, includes: a stacking process of forming an electrode by stacking a plurality of electrode layers on a semiconductor layer; and a anneal treatment process of treating the electrode. The stacking process including processes of forming a first electrode layer mainly made of aluminum (Al) as one of the plurality of electrode layers; forming a second electrode layer mainly made of a conductive material that has a higher melting point than that of aluminum (Al) and reacts with aluminum (Al) at 450° C. or higher temperature, as one of the plurality of electrode layers, on the first electrode layer; and forming a third electrode layer mainly made of palladium (Pd) as an electrode layer most distant from the semiconductor layer among the plurality of electrode layers, on the second electrode layer.Type: GrantFiled: September 14, 2015Date of Patent: February 28, 2017Assignee: TOYODA GOSEI CO., LTD.Inventors: Nariaki Tanaka, Tohru Oka
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Patent number: 9559218Abstract: A semiconductor device comprises a semiconductor layer including a mesa structure and a peripheral surface extending around the mesa structure, the mesa structure having a plateau shape with an upper surface and a side surface; a Schottky electrode forming a Schottky junction with the upper surface; an insulating film extending from the peripheral surface, across the side surface, and onto the Schottky electrode, the insulating film having an opening formed on the Schottky electrode; and a wiring electrode electrically connected to the Schottky electrode inside the opening, the wiring electrode extending from inside of the opening, across a portion of the insulating film formed on the side surface, and onto another portion of the insulating film formed on the peripheral surface.Type: GrantFiled: February 18, 2016Date of Patent: January 31, 2017Assignee: Toyoda Gosei Co., Ltd.Inventors: Kazuya Hasegawa, Tohru Oka, Nariaki Tanaka
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Publication number: 20160365421Abstract: A technique of improving the barrier height between an electrode layer and a semiconductor layer is provided. A semiconductor device comprises a semiconductor layer made of a semiconductor and an electrode layer formed to be at least partly in Schottky contact with the semiconductor layer. The electrode layer includes a first layer and a second layer arranged sequentially from a semiconductor layer-side. The first layer is a layer mainly made of nickel and has a film thickness of not less than 50 nm and not greater than 200 nm. The second layer is a layer mainly made of at least one metal selected from the group consisting of palladium, platinum and iridium. The second layer has a film thickness that is equal to or greater than the film thickness of the first layer.Type: ApplicationFiled: January 31, 2015Publication date: December 15, 2016Inventors: Kazuya HASEGAWA, Tohru Oka, Nariaki Tanaka
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Publication number: 20160284812Abstract: There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises a film formation process of forming a molybdenum layer that is mainly made of molybdenum (Mo), on at least one of a semiconductor layer, an insulating film and an electrode in the semiconductor device; a heat treatment process of heating the molybdenum layer at temperature of not lower than 200° C.; and a dry etching process of processing the semiconductor device that includes the formed molybdenum layer by dry etching, subsequent to the heat treatment process.Type: ApplicationFiled: March 7, 2016Publication date: September 29, 2016Inventors: Nariaki TANAKA, Tohru OKA
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Publication number: 20160276172Abstract: An object is to avoid an increase in contact resistance of an ohmic electrode by etching in a semiconductor device. There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises forming a semiconductor layer; forming an ohmic electrode by stacking a plurality of metal layers, on the semiconductor layer; forming another metal layer that is mainly made of another metal different from a material of an outermost layer among the plurality of metal layers, on the ohmic electrode; removing the another metal layer from top of the ohmic electrode by etching; and processing the ohmic electrode by heat treatment, subsequent to the etching.Type: ApplicationFiled: February 26, 2016Publication date: September 22, 2016Inventors: Tsutomu INA, Tohru OKA, Nariaki TANAKA
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Patent number: 9443950Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer.Type: GrantFiled: December 12, 2013Date of Patent: September 13, 2016Assignee: TOYODA GOSEI CO., LTD.Inventors: Toru Oka, Nariaki Tanaka
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Publication number: 20160254392Abstract: A semiconductor device comprises a semiconductor layer including a mesa structure and a peripheral surface extending around the mesa structure, the mesa structure having a plateau shape with an upper surface and a side surface; a Schottky electrode forming a Schottky junction with the upper surface; an insulating film extending from the peripheral surface, across the side surface, and onto the Schottky electrode, the insulating film having an opening formed on the Schottky electrode; and a wiring electrode electrically connected to the Schottky electrode inside the opening, the wiring electrode extending from inside of the opening, across a portion of the insulating film formed on the side surface, and onto another portion of the insulating film formed on the peripheral surface.Type: ApplicationFiled: February 18, 2016Publication date: September 1, 2016Inventors: Kazuya Hasegawa, Tohru Oka, Nariaki Tanaka
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Patent number: 9431260Abstract: There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing method comprises: a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction and make the plane in the thickness direction of the P-type semiconductor layer exposed; and a annealing process of annealing the P-type semiconductor layer in an atmosphere containing oxygen, after the dry etching process. This manufacturing method improves the electrical properties of the P-type semiconductor layer.Type: GrantFiled: December 8, 2014Date of Patent: August 30, 2016Assignee: Toyoda Gosei Co., Ltd.Inventors: Nariaki Tanaka, Tohru Oka
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Patent number: 9391150Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer; a first electrode layer; a second electrode layer; and a control electrode layer. The first and second electrode layers are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. The second electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, and is formed to be extended to a position on a control electrode layer side of the connection line.Type: GrantFiled: December 12, 2013Date of Patent: July 12, 2016Assignee: Toyoda Gosei Co., Ltd.Inventors: Toru Oka, Nariaki Tanaka
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Publication number: 20160163792Abstract: A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.Type: ApplicationFiled: December 3, 2015Publication date: June 9, 2016Inventors: Tohru OKA, Kazuya HASEGAWA, Noriaki MURAKAMI, Takahiro SONOYAMA, Nariaki TANAKA
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Patent number: 9331157Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, with a surface of the p-type semiconductor layer and with at least a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer.Type: GrantFiled: December 12, 2013Date of Patent: May 3, 2016Assignee: TOYODA GOSEI CO., LTD.Inventors: Toru Oka, Nariaki Tanaka
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Publication number: 20160087051Abstract: A manufacturing method of a semiconductor device, includes: a stacking process of forming an electrode by stacking a plurality of electrode layers on a semiconductor layer; and a anneal treatment process of treating the electrode. The stacking process including processes of forming a first electrode layer mainly made of aluminum (Al) as one of the plurality of electrode layers; forming a second electrode layer mainly made of a conductive material that has a higher melting point than that of aluminum (Al) and reacts with aluminum (Al) at 450° C. or higher temperature, as one of the plurality of electrode layers, on the first electrode layer; and forming a third electrode layer mainly made of palladium (Pd) as an electrode layer most distant from the semiconductor layer among the plurality of electrode layers, on the second electrode layer.Type: ApplicationFiled: September 14, 2015Publication date: March 24, 2016Inventors: Nariaki Tanaka, Tohru Oka
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Publication number: 20150295096Abstract: A technique of suppressing leak current in a semiconductor device is provided. A semiconductor device, comprises: a semiconductor layer made of a semiconductor; an insulating layer configured to have electric insulation property and formed to cover part of the semiconductor layer; a first electrode layer formed on the semiconductor layer, configured to have a work function of not less than 0.5 eV relative to electron affinity of the semiconductor layer and extended to surface of the insulating layer to form a field plate structure; and a second electrode layer configured to have electrical conductivity and formed to cover at least part of the first electrode layer. A distance between an edge of a part of the first electrode layer that is in contact with the semiconductor layer and the second electrode layer is equal to or greater than 0.2 ?m.Type: ApplicationFiled: February 2, 2015Publication date: October 15, 2015Inventors: Tohru OKA, Kazuya HASEGAWA, Nariaki TANAKA, Noriaki MURAKAMI
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Patent number: 9123635Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.Type: GrantFiled: December 12, 2013Date of Patent: September 1, 2015Assignee: TOYODA GOSEI CO., LTD.Inventors: Toru Oka, Nariaki Tanaka
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Publication number: 20150162208Abstract: There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing method comprises: a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction and make the plane in the thickness direction of the P-type semiconductor layer exposed; and a annealing process of annealing the P-type semiconductor layer in an atmosphere containing oxygen, after the dry etching process. This manufacturing method improves the electrical properties of the P-type semiconductor layer.Type: ApplicationFiled: December 8, 2014Publication date: June 11, 2015Inventors: Nariaki TANAKA, Tohru Oka
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Publication number: 20140167062Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: TOYODA GOSEI CO., LTD.Inventors: Toru Oka, NARIAKI TANAKA
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Publication number: 20140167061Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: TOYODA GOSEI CO., LTD.Inventors: Toru Oka, Nariaki Tanaka
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Publication number: 20140167147Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, with a surface of the p-type semiconductor layer and with at least a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: TOYODA GOSEI CO., LTD.Inventors: Toru Oka, Nariaki Tanaka
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Publication number: 20140167148Abstract: A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer; a first electrode layer; a second electrode layer; and a control electrode layer. The first and second electrode layers are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. The second electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, and is formed to be extended to a position on a control electrode layer side of the connection line.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: TOYODA GOSEI CO., LTD.Inventors: Toru Oka, Nariaki Tanaka