Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

Abstract: A process for performing a design rule check (DRC) by a computer may comprise receiving a DRC result comprising a plurality of DRC errors, the DRC result corresponding to a DRC deck comprising a plurality of rules and a design layout database comprising a plurality of components; classifying, using a neural network, each of the plurality of DRC errors according to whether that DRC should be ignored; and producing a final report including a plurality of respective indications of whether the plurality of DRC errors should be ignored. Performing the process may further include the receiving mistake feedback regarding the final report; updating, using the mistake feedback, a DRC result dataset comprising a plurality of dataset entries; and re-training the neural network using the updated DRC result dataset.

Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P-silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P? silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

Abstract: Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.

Abstract: Diagnostic instruments and methods of operating diagnostic instruments are provided. Methods of operating a diagnostic instrument includes providing the diagnostic instrument having one or more modules, wherein the one or more modules are configured to analyze specimens; providing a specimen sorter coupled to the diagnostic instrument; and sorting specimens into at least first group and a second group, wherein specimens in the first group are to be analyzed by at least one of the one or more modules, and specimens in the second group are not to be analyzed by any of the one or more modules. Other sorting methods and diagnostic instruments are provided.

Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.

Abstract: A system comprises a server configured for performing steps of receiving, from an acquirer financial institution for a merchant, details of a transaction and a common virtual payment token. The transaction details include details of the merchant. Identification details of a set of consumer payment instruments associated with the common virtual payment token are retrieved from a consumer database. The consumer payment instrument for the merchant is selected from the set of consumer payment instruments, based on the merchant details. Payment details of the selected consumer payment instrument are retrieved from the consumer database. The transaction is processed with the selected consumer payment instrument by communicating to an issuer financial institution for the selected consumer payment instrument, the transaction details and the payment details of the selected consumer payment instrument.

Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

Abstract: A system comprises a server configured for performing steps of receiving, from an acquirer financial institution for a merchant, details of a transaction and a common virtual payment token. The transaction details include details of the merchant. Identification details of a set of consumer payment instruments associated with the common virtual payment token are retrieved from a consumer database. The consumer payment instrument for the merchant is selected from the set of consumer payment instruments, based on the merchant details. Payment details of the selected consumer payment instrument are retrieved from the consumer database. The transaction is processed with the selected consumer payment instrument by communicating to an issuer financial institution for the selected consumer payment instrument, the transaction details and the payment details of the selected consumer payment instrument.

Abstract: Embodiments provide a method for facilitating a payment transaction at a POS terminal. The method includes receiving, by a server system associated with a payment network, a machine-readable code comprising information corresponding to a merchant and a dynamic token. The machine-readable code is valid for only a pre-defined interval. The method includes sending, by the server system, a notification associated with the machine-readable code received from the customer device, to a merchant device for approval of the payment transaction. The method further includes receiving, by the server system, a merchant defined transaction code from the merchant device in response to receipt of the notification at the merchant device. The merchant defined transaction code indicates a nature of the payment transaction. facilitating, by the server system, the payment transaction upon receipt of the merchant defined transaction code from the merchant device.

Abstract: The present disclosure generally relates to an electronic system, a computerized method, and a non-transitory computer-readable storage medium comprising instructions for processing a transaction between a consumer and a merchant with a payment instrument of the consumer selected for the merchant.

Abstract: Methods and server systems for facilitating sharing of reward points between users are disclosed. Information related to linked one or more social IDs of a first user to a payment account of the first user is received and stored in a mapping file. A request for reward points redemption is initiated by the second user in response to an offer to redeem a fixed number of reward points posted by the first user on a social media platform. A social ID used by the second user to initiate the request on the social media platform is identified. A transfer of the fixed number of reward points from the first user to the second user is facilitated based on the mapping file and the social ID of the second user.

Abstract: System and method for facilitating electronic payment on delivery of a product. The system includes a merchant device; a manufacturer device that is in communication with the merchant device; and a courier device that is in communication with the merchant device. The merchant device is configured to: receive, from an issuer device that is in communication with the merchant device, a pre-authorization code in response to a request for pre-authorization of a transaction corresponding to an electronic payment request for the product; and generate a first machine-readable code having encoded thereon at least the pre-authorization code and an identifier corresponding to the product. The manufacturer device is configured to generate a second machine-readable code having encoded thereon at least the pre-authorization code and the identifier corresponding to the product.

Abstract: An apparatus for processing electronic payment transactions is provided. The apparatus includes a computer processor and a data storage device, the data storage device having an incoming and an outgoing transaction initiation module including non-transitory instructions operative by the processor to receive an order indication at a payment intermediary server, the order indication indicating an order by a customer having an order value amount, initiate a transaction from an account associated with the customer to an intermediary account for the order value amount, initiate a transaction from the intermediary account to an account associated with the merchant for a first portion of the order value amount, receive an order feedback indication, and initiate a further transaction or further transactions in response to the order feedback indication to transfer the second portion of the order value amount to the account associated with the merchant and/or the account associated with the customer.

Abstract: The disclosure provides integrated circuit (IC) layouts and methods to form the same. An IC layout may include two standard cells, with a well contact cell laterally between them. The well contact cell may include a single semiconductor region having the first doping type, an active bridge region within the single semiconductor region, extending continuously from the first active region of the first standard cell to the third active region of the second standard cell. A doped tap region within the single semiconductor region is laterally separated from the active bridge region. The doped tap region is laterally aligned with the second active region and the fourth active region.

Abstract: Disclosed is a system for executing a computer process for processing a transaction. The system comprises a point-of-sale (POS) terminal, and an application support terminal (AST). The POS terminal comprises a POS processor and a POS memory device in communication with the POS processor and storing POS program instructions thereon. The POS processor is operative with the POS program instructions to receive transaction information comprising payment vehicle credentials of a payment vehicle for use in processing the transaction, and transaction details defining the transaction. The POS processor is further operative to determine, based on the transaction information, that the POS terminal cannot process the transaction, send the transaction information to the AST, the AST comprising an AST processor, and an AST memory device in communication with the AST processor and storing an application capable of processing the transaction using the payment vehicle credentials, and AST program instructions thereon.

Abstract: An apparatus for processing electronic payment transactions is provided. The apparatus includes a computer processor and a data storage device, the data storage device having an incoming and an outgoing transaction initiation module including non-transitory instructions operative by the processor to receive an order indication at a payment intermediary server, the order indication indicating an order by a customer having an order value amount, initiate a transaction from an account associated with the customer to an intermediary account for the order value amount, initiate a transaction from the intermediary account to an account associated with the merchant for a first portion of the order value amount, receive an order feedback indication, and initiate a further transaction or further transactions in response to the order feedback indication to transfer the second portion of the order value amount to the account associated with the merchant and/or the account associated with the customer.