Patents by Inventor Navneet Jain

Navneet Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190333853
    Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.
    Type: Application
    Filed: May 14, 2019
    Publication date: October 31, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Juhan Kim, Mahbub Rashed, Navneet Jain
  • Publication number: 20190325438
    Abstract: A system and method for completing a transaction initiated at a payment terminal are provided. The method comprises receiving, from the payment terminal, transaction data relating to the transaction, the transaction data including account details identifying an account and an issuer managing the account; determining if the issuer corresponds to the same entity in response to the receipt of the transaction data; and forwarding, to a payment network server, an approval message that is received from an issuer server corresponding to the issuer when it is determined that the issuer corresponds to the same entity, the approval message approving the transaction.
    Type: Application
    Filed: March 11, 2019
    Publication date: October 24, 2019
    Applicant: Mastercard International Incorporated
    Inventors: Ravinder Wadhwa, Piyush Sharma, Navneet Jain
  • Publication number: 20190295115
    Abstract: A voucher redemption method includes redeeming a voucher against a previous purchase based on a voucher-redemption request. The voucher-redemption request includes a voucher identifier of the voucher, an account identifier of an account, and a purchase order identifier associated with the previous purchase. The voucher is validated based on the voucher identifier and the purchase order identifier. When the voucher is valid, a voucher amount associated with the voucher is credited to the account specified in the voucher-redemption request. Hence, the voucher is redeemed.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 26, 2019
    Applicant: Mastercard International Incorporated
    Inventors: Piyush Sharma, Ravinder Wadhwa, Navneet Jain
  • Publication number: 20190295072
    Abstract: A transaction authorization method includes generation of a unique identification code for registering a user as an on-behalf payee for an account based on a registration request raised by an account holder of the account. The user is authorized to perform on-behalf transactions from the account by using the unique identification code. The account holder is notified, when the user performs an on-behalf transaction from the account. The on-behalf transaction is authorized, when the account holder approves the on-behalf transaction and is declined, when the account holder rejects the on-behalf transaction.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 26, 2019
    Inventors: Navneet Jain, Ganesh Shinde, Ravi Pareek
  • Patent number: 10366954
    Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juhan Kim, Mahbub Rashed, Navneet Jain
  • Patent number: 10360334
    Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Navneet Jain, Mahbub Rashed, Juhan Kim
  • Publication number: 20190197576
    Abstract: The present disclosure generally relates to an electronic system, a computerized method, and a non-transitory computer-readable storage medium for a merchant to rebate customers. The system comprises a merchant server communicatively linked to a payment network.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Applicant: Mastercard International Incorporated
    Inventors: Navneet JAIN, Piyush SHARMA, Puneet GANDHI
  • Patent number: 10333497
    Abstract: A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anil Kumar, Mahbub Rashed, Sushama Davar, Navneet Jain
  • Patent number: 10303196
    Abstract: Disclosed is a voltage generator that includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit is selectively operable in a single trimming mode enabling positive trimming only or in a dual trimming mode that shifts the voltage range downward enabling a somewhat smaller amount of positive trimming and also some negative trimming. The second voltage generation circuit is selectively operable in a single trimming mode enabling negative trimming only or in a dual trimming mode that shifts the voltage range upward enabling a somewhat smaller amount of negative trimming and also some positive trimming. Also disclosed is an integrated circuit (IC) chip that incorporates one or more such voltage generators for back-biasing the field effect transistors in one or more circuit blocks, respectively.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Navneet Jain, Arif A. Siddiqi, Mahbub Rashed
  • Publication number: 20190122216
    Abstract: System and method for facilitating electronic payment on delivery of a product. The system includes a merchant device; a manufacturer device that is in communication with the merchant device; and a courier device that is in communication with the merchant device. The merchant device is configured to: receive, from an issuer device that is in communication with the merchant device, a pre-authorization code in response to a request for pre-authorization of a transaction corresponding to an electronic payment request for the product; and generate a first machine-readable code having encoded thereon at least the pre-authorization code and an identifier corresponding to the product. The manufacturer device is configured to generate a second machine-readable code having encoded thereon at least the pre-authorization code and the identifier corresponding to the product.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 25, 2019
    Applicant: Mastercard International Incorporated
    Inventors: Navneet Jain, Arunmurthy Gurunathan, Sonal Vishwas Khanvilkar, Rohit Mali
  • Publication number: 20190114633
    Abstract: A payment network server for processing a payment card transaction is described.
    Type: Application
    Filed: September 7, 2018
    Publication date: April 18, 2019
    Inventors: Puneet Gandhi, Arunmurthy Gurunathan, Navneet Jain
  • Publication number: 20190114607
    Abstract: Disclosed is a system for executing a computer process for processing a transaction. The system comprises a point-of-sale (POS) terminal, and an application support terminal (AST). The POS terminal comprises a POS processor and a POS memory device in communication with the POS processor and storing POS program instructions thereon. The POS processor is operative with the POS program instructions to receive transaction information comprising payment vehicle credentials of a payment vehicle for use in processing the transaction, and transaction details defining the transaction. The POS processor is further operative to determine, based on the transaction information, that the POS terminal cannot process the transaction, send the transaction information to the AST, the AST comprising an AST processor, and an AST memory device in communication with the AST processor and storing an application capable of processing the transaction using the payment vehicle credentials, and AST program instructions thereon.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 18, 2019
    Applicant: Mastercard International Incorporated
    Inventors: Ravinder WADHWA, Piyush SHARMA, Navneet JAIN
  • Publication number: 20190066147
    Abstract: A computer implemented method for delivering one or more incentives from one or more merchant devices to a client device, the client device being associated with a user, the computer implemented method comprising determining proximity between the client device and the one or more merchant devices, the proximity being determined based on a distance between the client device and the one or more merchant devices being within a predetermined threshold, querying, based on such determination, a loyalty database to identify an association status between the client device and the one or more merchant devices and providing the one or more incentives to the client device based on the association status.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 28, 2019
    Inventors: Navneet Jain, Sonal Vishwas Khanvilkar, Arunmurthy Gurunathan
  • Publication number: 20190043053
    Abstract: A transaction authorization method and system for performing an authorization for a transaction are provided. The transaction authorization method includes receiving by a first server, a first request from a second server for initiating authorization for a transaction at a first time instance, when a user uses a first transaction card to initiate the transaction. A first set of parameters is associated with the first transaction card. The first server receives a second request for completing the authorization for the transaction at a second time instance, when the user uses a second transaction card to complete the transaction. A second set of parameters is associated with the second transaction card. The first server authorizes the transaction based on a match between the first set of parameters and the second set of parameters.
    Type: Application
    Filed: July 16, 2018
    Publication date: February 7, 2019
    Inventors: Navneet Jain, Piyush Sharma
  • Patent number: 10199378
    Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Navneet Jain, Juhan Kim, Andy Nguyen, Mahbub Rashed
  • Publication number: 20180336535
    Abstract: An apparatus for processing electronic payment transactions is provided. The apparatus includes a computer processor and a data storage device, the data storage device having an incoming and an outgoing transaction initiation module including non-transitory instructions operative by the processor to receive an order indication at a payment intermediary server, the order indication indicating an order by a customer having an order value amount, initiate a transaction from an account associated with the customer to an intermediary account for the order value amount, initiate a transaction from the intermediary account to an account associated with the merchant for a first portion of the order value amount, receive an order feedback indication, and initiate a further transaction or further transactions in response to the order feedback indication to transfer the second portion of the order value amount to the account associated with the merchant and/or the account associated with the customer.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 22, 2018
    Inventors: Arunmurthy Gurunathan, Navneet Jain
  • Publication number: 20180293568
    Abstract: The present disclosure generally relates to an electronic system and method for managing usage of resources in a merchant facility. The system comprises a server and a merchant communication device, where the server is configured to receive, from the merchant communication device, identification details of a consumer from a wearable device during a first communication; communicate merchant data from the merchant communication device to the consumer wearable device upon receipt of the consumer identification details; receive, via the merchant communication device, resource usage data provided by the wearable device during a second communication; and receive a payment confirmation message upon transfer of an aggregated cost from a payment instrument of the consumer to the merchant financial account, wherein usage of the resources is tracked by the wearable device, and the aggregated cost is determined by the wearable device based on the tracked usage and rate details of the resources.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 11, 2018
    Inventors: Arunmurthy Gurunathan, Navneet Jain
  • Patent number: 10096595
    Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: October 9, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Juhan Kim, Mahbub Rashed, Navneet Jain, Anurag Mittal, Sangmoon Kim
  • Patent number: 10068918
    Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christian Haufe, Ingolf Lorenz, Michael Zier, Ulrich Gerhard Hensel, Navneet Jain
  • Publication number: 20180225406
    Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.
    Type: Application
    Filed: February 9, 2017
    Publication date: August 9, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Navneet Jain, Mahbub Rashed, Juhan Kim