Abstract: A system for processing payment, comprising: a processor module in communication with a point-of-sale (POS) terminal and a payment module, wherein the processor module is configured to: (i) receive, from the POS terminal: a first set of characters that is a proxy for a first account number associated with a fund recipient's account; a second set of characters that is a proxy for a second account number associated with a fund sender's account; and an amount of funds requested by the fund recipient from the fund sender for payment; (ii) convert: the first set of characters into the first account number; the second set of characters into the second account number; and (iii) transmit, to the payment module: the first and second account numbers; and an instruction to deduct the amount of funds requested by the fund recipient from the fund sender's account that is associated with the second account number.

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract: The present disclosure provides an integrated circuit product including a plurality of standard cells, each standard cell of the plurality of standard cells being in abutment with at least one other standard cell of the plurality of standard cells, a continuous active region continuously extending across the plurality of standard cells, at least two active regions being separated by an intermediate diffusion break, wherein each standard cell comprises at least one PMOS device and at least one NMOS device, the at least one PMOS device being provided in and above the continuous active region and the at least one NMOS device being provided in and above the at least two active regions.

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

Abstract: Methodologies and an apparatus for measuring setup and hold times of fabricated semiconductor devices are provided. Embodiments include: providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time or hold time of a device under test are generated.

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract: Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions.

Abstract: Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.

Abstract: Methodologies and an apparatus for measuring setup and hold times of fabricated semiconductor devices are provided. Embodiments include: providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time or hold time of a device under test are generated.

Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Abstract: A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Abstract: Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.

Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.