Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.

Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame.

Abstract: A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

Abstract: In described examples, a circuit (e.g., an integrated circuit) includes a semiconductor substrate that includes a frontside surface and a backside surface. A circuit element is included at the frontside surface. An optional electrical insulator layer can be included adjacent to the backside surface. A distributor layer is included adjacent to the backside surface. In some examples, the distributor layer includes a distributor material that includes a matrix of cohered nanoparticles and metallic particles embedded by the cohered nanoparticles.

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

Abstract: A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate to permit electroplating. In addition, the method may be used to directly connect a semiconductor die to the metal substrate of the package.

Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

Abstract: A microelectronic device has a solder-free package lead extending through an electrically non-conductive package structure to an exterior of the microelectronic device. The package lead includes a pillar contacting a terminal on a die and extending partway through the package structure, and an external lead electrically coupled to the pillar and extending to an exterior of the microelectronic device. The package lead is free of a solder joint. The microelectronic device may be formed by forming an access cavity package structure, to expose the pillar, and forming the external lead by a plating process. The microelectronic device may be formed by providing an external lead lamina containing the external lead, and forming a plated metal joint by a plating process that connects the external lead to the pillar.

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

Abstract: A die includes a semiconductor layer, an electrical contact on a first side of the semiconductor layer, a backside electrical contact layer on second side of the semiconductor layer. The die further includes a zinc layer over at least one of the electrical contact or the backside electrical contact layer of the die, and a conversion coating over the zinc layer. The conversion coating includes at least one of zirconium and vanadium. As part of an embedded die package including the die, at least a portion of the conversion coating may adjacent to an electrically insulating substrate of the embedded die package.

Abstract: A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.

Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

Abstract: An integrated circuit (IC) includes a substrate with a semiconductor surface layer including circuitry configured for realizing at least one circuit function including a plurality of transistors, including at least one dielectric layer having a first and a second through-via over the plurality of transistors. The through-vias include a first top level via and at least a second top level via lateral to the first top level via. A composite layer includes copper (Cu), a first metal including zinc, and a second metal, wherein the composite layer is on a barrier layer that is on the first top level via and on the second top level. A plurality of Cu traces includes a first Cu top metal trace on the composite layer contacting the first top level via and a second Cu metal trace on the composite layer contacting the second top level via.

Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.