Patents by Inventor Neil Buxton
Neil Buxton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966605Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including a non-volatile storage including a superblock and a controller configured to notify a host of a size of the superblock to a host, determine a stream that aligns with the superblock, write data corresponding to the stream to the superblock, and determine that writing the data correspond to the stream has completed.Type: GrantFiled: March 9, 2022Date of Patent: April 23, 2024Assignee: KIOXIA CORPORATIONInventors: Steven Wells, Neil Buxton, Nigel Horspool, Mohinder Saluja, Paul Suhler
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Patent number: 11923025Abstract: Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command and setting row-based programming parameters for the target row using target physical device parameters of the target row and optimized programming parameters corresponding to the physical device parameters.Type: GrantFiled: December 22, 2020Date of Patent: March 5, 2024Assignee: KIOXIA CORPORATIONInventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa, Neil Buxton
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Patent number: 11914898Abstract: Various implementations described herein relate to creating a namespace in response to determining that a sum of namespace sizes of a plurality of namespaces is less than a first threshold for the point of thin-provisioning. A write command and data are received from a host. The write command and the data are received in response to determining that a sum of namespace utilization of the plurality of namespaces is less than a second threshold. The data is compressed and stored in the created namespace.Type: GrantFiled: January 26, 2022Date of Patent: February 27, 2024Assignee: KIOXIA CORPORATIONInventors: Steven Wells, Neil Buxton
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Patent number: 11797452Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.Type: GrantFiled: July 18, 2022Date of Patent: October 24, 2023Assignee: KIOXIA CORPORATIONInventors: Saswati Das, Manish Kadam, Neil Buxton
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Publication number: 20230305752Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.Type: ApplicationFiled: June 1, 2023Publication date: September 28, 2023Inventors: Neil Buxton, Avadhani Shridhar, Steven Wells, Nicole Ross
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Publication number: 20230305745Abstract: Various implementations described herein relate to systems, methods, and non-transitory computer-readable media for managing write commands to superblocks, including receiving, by a storage device from a host, a write command and a write data. The write command indicates that the write data is to be written to a first superblock of the storage device. The storage device determines the first superblock lacks sufficient capacity to store the write data. In response to determining that the first superblock lacks the sufficient capacity to store the write data, the storage device programs the write data to at least one of a reserved capacity of the first superblock or a second superblock.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Nigel Horspool, Steve Wells, Neil Buxton
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Publication number: 20230289078Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including a non-volatile storage including a superblock and a controller configured to notify a host of a size of the superblock to a host, determine a stream that aligns with the superblock, write data corresponding to the stream to the superblock, and determine that writing the data correspond to the stream has completed.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Inventors: Steven Wells, Neil Buxton, Nigel Horspool, Mohinder Saluja, Paul Suhler
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Patent number: 11727998Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: GrantFiled: October 27, 2021Date of Patent: August 15, 2023Assignee: Kioxia CorporationInventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
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Publication number: 20230236763Abstract: Various implementations described herein relate to creating a namespace in response to determining that a sum of namespace sizes of a plurality of namespaces is less than a first threshold for the point of thin-provisioning. A write command and data are received from a host. The write command and the data are received in response to determining that a sum of namespace utilization of the plurality of namespaces is less than a second threshold. The data is compressed and stored in the created namespace.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Applicant: Kioxia CorporationInventors: Steven Wells, Neil Buxton
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Publication number: 20230229326Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including determining superblocks, including first and second superblocks, in a non-volatile memory storage. The non-volatile memory storage includes independent locations that may be planes or dies. The first superblock includes first blocks corresponding to first independent locations, and the second superblock includes second blocks corresponding to second independent locations. A first number of the first independent locations is less than a number of the independent locations. A second number of the second plurality of independent locations is less than the number of the independent locations.Type: ApplicationFiled: January 18, 2022Publication date: July 20, 2023Applicant: Kioxia CorporationInventors: Neil Buxton, Steven Wells
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Patent number: 11704061Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.Type: GrantFiled: March 16, 2021Date of Patent: July 18, 2023Assignee: Kioxia CorporationInventors: Neil Buxton, Avadhani Shridhar, Steven Wells, Nicole Ross
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Patent number: 11662942Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller is configured to issue a command to the non-volatile semiconductor memory device specifying a subset of n buffers of the plurality of buffers in which to transfer a data payload relating to the command.Type: GrantFiled: March 16, 2021Date of Patent: May 30, 2023Assignee: Kioxia CorporationInventors: Avadhani Shridhar, Neil Buxton, Steven Wells, Nicole Ross
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Publication number: 20230153024Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.Type: ApplicationFiled: January 13, 2023Publication date: May 18, 2023Applicant: Kioxia CorporationInventors: Avadhani SHRIDHAR, Neil BUXTON
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Patent number: 11556272Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.Type: GrantFiled: September 18, 2020Date of Patent: January 17, 2023Assignee: KIOXIA CORPORATIONInventors: Avadhani Shridhar, Neil Buxton
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Publication number: 20220350746Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Applicant: Kioxia CorporationInventors: Saswati Das, Manish Kadam, Neil Buxton
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Patent number: 11482294Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.Type: GrantFiled: June 1, 2021Date of Patent: October 25, 2022Assignee: Kioxia CorporationInventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
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Publication number: 20220300194Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller is configured to issue a command to the non-volatile semiconductor memory device specifying a subset of n buffers of the plurality of buffers in which to transfer a data payload relating to the command.Type: ApplicationFiled: March 16, 2021Publication date: September 22, 2022Inventors: Avadhani Shridhar, Neil Buxton, Steven Wells, Nicole Ross
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Publication number: 20220300199Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.Type: ApplicationFiled: March 16, 2021Publication date: September 22, 2022Inventors: Neil Buxton, Avadhani Shridhar, Steven Wells, Nicole Ross
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Patent number: 11392499Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.Type: GrantFiled: September 18, 2020Date of Patent: July 19, 2022Assignee: KIOXIA CORPORATIONInventors: Saswati Das, Manish Kadam, Neil Buxton
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Publication number: 20220199183Abstract: Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command and setting row-based programming parameters for the target row using target physical device parameters of the target row and optimized programming parameters corresponding to the physical device parameters.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Applicant: Kioxia CorporationInventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa, Neil Buxton