Patents by Inventor Neil Buxton

Neil Buxton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220300194
    Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller is configured to issue a command to the non-volatile semiconductor memory device specifying a subset of n buffers of the plurality of buffers in which to transfer a data payload relating to the command.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Avadhani Shridhar, Neil Buxton, Steven Wells, Nicole Ross
  • Publication number: 20220300199
    Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Inventors: Neil Buxton, Avadhani Shridhar, Steven Wells, Nicole Ross
  • Patent number: 11392499
    Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: July 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Saswati Das, Manish Kadam, Neil Buxton
  • Publication number: 20220199183
    Abstract: Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command and setting row-based programming parameters for the target row using target physical device parameters of the target row and optimized programming parameters corresponding to the physical device parameters.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: Kioxia Corporation
    Inventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa, Neil Buxton
  • Patent number: 11321022
    Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes requesting power credits while performing a program or erase operation for a flash memory of the SSD. In response to determining that the requested power credits are rejected, the program or erase operation is suspended and its power credits are released. A read operation may then be performed in response to suspending the program or erase operation and releasing its power credits.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: May 3, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Neil Buxton, Gary James Calder
  • Publication number: 20220091984
    Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Saswati DAS, Manish KADAM, Neil BUXTON
  • Publication number: 20220091775
    Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Avadhani SHRIDHAR, Neil BUXTON
  • Publication number: 20220051736
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Shigehiro ASANO, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
  • Patent number: 11189353
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: November 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
  • Publication number: 20210287756
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Publication number: 20210200481
    Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes requesting power credits while performing a program or erase operation for a flash memory of the SSD. In response to determining that the requested power credits are rejected, the program or erase operation is suspended and its power credits are released. A read operation may then be performed in response to suspending the program or erase operation and releasing its power credits.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: Kioxia Corporation
    Inventors: Neil BUXTON, Gary James CALDER
  • Patent number: 11049581
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Patent number: 10996870
    Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 4, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Neil Buxton
  • Publication number: 20210020253
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Inventors: Shigehiro ASANO, Neil BUXTON, Julien MARGETTS, Shunichi IGAHARA, Takehiko AMAKI
  • Patent number: 10854302
    Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
  • Publication number: 20200303029
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 24, 2020
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Publication number: 20200278800
    Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 3, 2020
    Inventor: Neil Buxton
  • Patent number: 10628081
    Abstract: In one embodiment, a method for reducing the variance in latency of host I/O commands by managing non-host command queues in a solid state storage drive comprises receiving a plurality of non-host commands in at least one non-host command queue, each of the plurality of non-host commands configured to be executed by one of a plurality of non-volatile memory dies, and issuing a non-host command from the at least one non-host command queue to one of the plurality of non-volatile memory dies when a latency-reducing condition is satisfied. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a present number of active non-host commands is less than a first maximum number of active non-host commands. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a latency cost of the non-host command is less than or equal to an available latency budget.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Steven Wells, Neil Buxton
  • Publication number: 20200105359
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
  • Patent number: 10607712
    Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson