Patents by Inventor Neil Buxton
Neil Buxton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11321022Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes requesting power credits while performing a program or erase operation for a flash memory of the SSD. In response to determining that the requested power credits are rejected, the program or erase operation is suspended and its power credits are released. A read operation may then be performed in response to suspending the program or erase operation and releasing its power credits.Type: GrantFiled: December 31, 2019Date of Patent: May 3, 2022Assignee: KIOXIA CORPORATIONInventors: Neil Buxton, Gary James Calder
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Publication number: 20220091984Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Saswati DAS, Manish KADAM, Neil BUXTON
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Publication number: 20220091775Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Avadhani SHRIDHAR, Neil BUXTON
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Publication number: 20220051736Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: ApplicationFiled: October 27, 2021Publication date: February 17, 2022Inventors: Shigehiro ASANO, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
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Patent number: 11189353Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: GrantFiled: October 1, 2020Date of Patent: November 30, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
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Publication number: 20210287756Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
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Publication number: 20210200481Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes requesting power credits while performing a program or erase operation for a flash memory of the SSD. In response to determining that the requested power credits are rejected, the program or erase operation is suspended and its power credits are released. A read operation may then be performed in response to suspending the program or erase operation and releasing its power credits.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Applicant: Kioxia CorporationInventors: Neil BUXTON, Gary James CALDER
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Patent number: 11049581Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.Type: GrantFiled: March 6, 2020Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
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Patent number: 10996870Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.Type: GrantFiled: March 6, 2020Date of Patent: May 4, 2021Assignee: Toshiba Memory CorporationInventor: Neil Buxton
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Publication number: 20210020253Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: ApplicationFiled: October 1, 2020Publication date: January 21, 2021Inventors: Shigehiro ASANO, Neil BUXTON, Julien MARGETTS, Shunichi IGAHARA, Takehiko AMAKI
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Patent number: 10854302Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: GrantFiled: October 12, 2018Date of Patent: December 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shigehiro Asano, Neil Buxton, Julien Margetts, Shunichi Igahara, Takehiko Amaki
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Publication number: 20200303029Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.Type: ApplicationFiled: March 6, 2020Publication date: September 24, 2020Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
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Publication number: 20200278800Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.Type: ApplicationFiled: March 6, 2020Publication date: September 3, 2020Inventor: Neil Buxton
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Patent number: 10628081Abstract: In one embodiment, a method for reducing the variance in latency of host I/O commands by managing non-host command queues in a solid state storage drive comprises receiving a plurality of non-host commands in at least one non-host command queue, each of the plurality of non-host commands configured to be executed by one of a plurality of non-volatile memory dies, and issuing a non-host command from the at least one non-host command queue to one of the plurality of non-volatile memory dies when a latency-reducing condition is satisfied. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a present number of active non-host commands is less than a first maximum number of active non-host commands. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a latency cost of the non-host command is less than or equal to an available latency budget.Type: GrantFiled: March 9, 2018Date of Patent: April 21, 2020Assignee: Toshiba Memory CorporationInventors: Steven Wells, Neil Buxton
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Publication number: 20200105359Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
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Patent number: 10607712Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.Type: GrantFiled: September 28, 2018Date of Patent: March 31, 2020Assignee: Toshiba Memory CorporationInventors: Neil Buxton, Shigehiro Asano, Steven Wells, Mark Carlson
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Patent number: 10599346Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.Type: GrantFiled: November 12, 2018Date of Patent: March 24, 2020Assignee: Toshiba Memory CorporationInventor: Neil Buxton
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Publication number: 20190287632Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.Type: ApplicationFiled: October 12, 2018Publication date: September 19, 2019Inventors: Shigehiro ASANO, Neil BUXTON, Julien MARGETTS, Shunichi IGAHARA, Takehiko AMAKI
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Publication number: 20190278515Abstract: In one embodiment, a method for reducing the variance in latency of host I/O commands by managing non-host command queues in a solid state storage drive comprises receiving a plurality of non-host commands in at least one non-host command queue, each of the plurality of non-host commands configured to be executed by one of a plurality of non-volatile memory dies, and issuing a non-host command from the at least one non-host command queue to one of the plurality of non-volatile memory dies when a latency-reducing condition is satisfied. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a present number of active non-host commands is less than a first maximum number of active non-host commands. In one embodiment, the method further comprises determining that the latency-reducing condition is satisfied if a latency cost of the non-host command is less than or equal to an available latency budget.Type: ApplicationFiled: March 9, 2018Publication date: September 12, 2019Inventors: Steven Wells, Neil Buxton
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Patent number: 10404279Abstract: A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values.Type: GrantFiled: September 21, 2018Date of Patent: September 3, 2019Assignee: Toshiba Memory CorporationInventors: Paul Edward Hanham, David Malcolm Symons, Neil Buxton