Patents by Inventor Nian Niles Yang

Nian Niles Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210240358
    Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 5, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Sahil Sharma, Nian Niles Yang, Phil Reusswig, Rohit Sehgal, Piyush A. Dhotre
  • Patent number: 11016545
    Abstract: The present disclosure discloses a memory device including a control system for thermal throttling. The control system acquires the temperature of a non-volatile memory element from a temperature detector at a first frequency. Upon determining that the temperature of the non-volatile memory element is above a pre-determined threshold, the control system acquires the temperature of the non-volatile memory element from the temperature detector at a second frequency that is higher than the first frequency and activates the thermal throttling for the non-volatile memory element.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 25, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nian Niles Yang, Dmitry Vaysman, Eran Erez, Grishma Shah
  • Patent number: 10896123
    Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 19, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Sahil Sharma, Philip Reusswig, Rohit Sehgal
  • Publication number: 20200401207
    Abstract: For solid state drive (SSD) or other memory system formed of multiple memory dies, techniques are presented for operation in a standby mode with increased power savings. The memory dies are operable in a regular standby mode and in a low power standby mode. Based upon the amount of current each of the memory dies in the regular standby mode, when the device goes into standby the memory dies that draw higher amounts of current when in the regular standby mode are instead placed into the low power standby mode. The amount of current drawn by each of the memory die in the regular standby mode can be determined for each of the memory dies at die sort or as part of the memory test process, or can be determine by an assembled SSD itself.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Dmitry Vaysman, Ekram Bhuiyan
  • Patent number: 10839914
    Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 17, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
    Inventors: Zhenlei Z. Shen, Nian Niles Yang, Gautham Reddy
  • Patent number: 10732856
    Abstract: An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Nian Niles Yang, Alexandra Bauche
  • Publication number: 20200225852
    Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Eran SHARON, Nian Niles YANG, Idan ALROD, Evgeny MEKHANIK, Mark SHLICK, Joanna LAI
  • Patent number: 10698610
    Abstract: A storage system and method for performing high-speed read and write operations are disclosed. In general, these embodiments discuss ways for performing a fast read in response to determining that the fast read will probably not have a negative impact on performance due to error correction and performing a fast write in response to determining that a storage system criterion is satisfied.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: June 30, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Nian Niles Yang
  • Publication number: 20200192791
    Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Sahil Sharma, Philip Reusswig, Rohit Sehgal
  • Patent number: 10642510
    Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Eran Sharon, Nian Niles Yang, Idan Alrod, Evgeny Mekhanik, Mark Shlick, Joanna Lai
  • Patent number: 10636504
    Abstract: Over a period of operation, non-volatile memory can develop a residual resistance that is impractical to remove. For example, in a NAND string of memory cells, trapped charge may build up in a region between the bit lines and drain side select gates, so that even when all the devices of a NAND string are in an “on” state, the NAND string will not conduct. This effect will skew both hard bit data determinations, indicating the data state of a selected memory cell, and soft bit data determinations which may correlate to the reliability of the hard bit data. Techniques are described to factor in such excessive residual resistance when determining the soft bit data.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Philip David Reusswig, Nian Niles Yang, Anubhav Khandelwal
  • Patent number: 10629260
    Abstract: A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 21, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Nian Niles Yang, Abhijeet Manohar
  • Patent number: 10573397
    Abstract: On a non-volatile memory circuit, peripheral circuitry generates programming voltages based on parameter values. If parameter values are incorrectly translated into programming voltages, data may be over-programmed, resulting in high bit error rates (BERs). The memory system can monitor the error rates using memory cell voltage distributions for different portions of the memory and look for signatures of such incorrect implementation. For example, by monitoring the BER along word lines that are most prone to error due to incorrectly implemented programming parameters, the memory system can determine if the programming parameters for the corresponding portion of a memory device indicate such anomalous behavior. If such a signature is found, the memory system checks to see whether the programming parameters should be adjusted, such as by comparing the programming parameters used on one die to programming parameters used on another die of the memory system, and adjust the programming parameters accordingly.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 25, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rohit Sehgal, Sahil Sharma, Philip Reusswig, Nian Niles Yang
  • Patent number: 10515008
    Abstract: Blocks of memory cells may be selected for use based on one or more measured performance characteristics that may include, but are not limited to, programming time or fail bit count. Blocks may be placed into a single level cell (SLC) block pool and one or more multi-level cell (MLC) block pools based on measured performance characteristic(s). For example, blocks that have a better SLC performance may be placed into the SLC block pool. Blocks may be targeted for garbage collection based on one or more measured performance characteristics. For example, blocks within an SLC block pool may be targeted for garbage collection based on a performance ranking of the SLC blocks, blocks within an MLC block pool may be targeted for garbage collection based on a performance ranking of the MLC blocks. Thus, the better performing blocks may be used more frequently, thereby improving performance.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 24, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rohit Sehgal, Nian Niles Yang
  • Patent number: 10482986
    Abstract: Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 19, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao-Han Cheng, Nian Niles Yang, Anubhav Khandelwal, Chung-Yao Pai
  • Patent number: 10452471
    Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: October 22, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zhenlei Shen, Nian Niles Yang, Chao-Han Cheng
  • Patent number: 10402117
    Abstract: A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: September 3, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nian Niles Yang, Idan Alrod
  • Publication number: 20190265888
    Abstract: A storage system and method for performing high-speed read and write operations are disclosed. In general, these embodiments discuss ways for performing a fast read in response to determining that the fast read will probably not have a negative impact on performance due to error correction and performing a fast write in response to determining that a storage system criterion is satisfied.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventor: Nian Niles Yang
  • Publication number: 20190252025
    Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Zhenlei Z. Shen, Nian Niles Yang, Gautham Reddy
  • Patent number: 10379754
    Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.
    Type: Grant
    Filed: January 20, 2018
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Philip David Reusswig, Nian Niles Yang, Grishma Shah, Deepak Raghu, Preeti Yadav, Prasanna Desai Sudhir Rao, Smita Aggarwal, Dana Lee