Abstract: Blocks of memory cells may be selected for use based on one or more measured performance characteristics that may include, but are not limited to, programming time or fail bit count. Blocks may be placed into a single level cell (SLC) block pool and one or more multi-level cell (MLC) block pools based on measured performance characteristic(s). For example, blocks that have a better SLC performance may be placed into the SLC block pool. Blocks may be targeted for garbage collection based on one or more measured performance characteristics. For example, blocks within an SLC block pool may be targeted for garbage collection based on a performance ranking of the SLC blocks, blocks within an MLC block pool may be targeted for garbage collection based on a performance ranking of the MLC blocks. Thus, the better performing blocks may be used more frequently, thereby improving performance.

Abstract: Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.

Abstract: A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.

Abstract: A storage system and method for performing high-speed read and write operations are disclosed. In general, these embodiments discuss ways for performing a fast read in response to determining that the fast read will probably not have a negative impact on performance due to error correction and performing a fast write in response to determining that a storage system criterion is satisfied.

Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.

Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.

Abstract: The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an uncertainty prediction circuit coupled to the memory cells, and a data conversion circuit coupled to the memory cells. The uncertainty prediction circuit is configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state. The data conversion circuit is configured to apply a data conversion to a portion of data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing a group read refresh. An apparatus includes a plurality of memory groups. An apparatus includes an operation circuit that performs an operation on a selected memory group of a plurality of memory groups. An apparatus includes a remediation circuit that performs a countermeasure operation on an unselected memory group of a plurality of memory groups in response to an operation on a selected memory group.

Abstract: A storage system and method for reducing XOR recovery time are provided. In one embodiment, a storage system is provides comprising a memory and a controller. The controller is configured to generate a first exclusive-or (XOR) parity for pages of data written to the memory; after the first XOR parity has been generated, determine that there is at least one page of invalid data in the pages of data written to the memory; and generate a second XOR parity for the pages of data that excludes the at least one page of invalid data, wherein the second XOR parity is generated by performing an XOR operation using the first XOR parity and the at least one page of invalid data as inputs. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.

Abstract: A memory device including a controller for handling thermal shutdown of the memory device. The control system acquires temperatures of a plurality of non-volatile memory elements in the memory device from one or more temperature detectors at a first frequency. Upon determining that the temperature of one of the plurality of non-volatile memory elements is above a threshold, the controller activates thermal throttling for the plurality of non-volatile memory elements and flushes metadata from a volatile memory element in the memory device to the plurality of non-volatile memory elements for future recovery of the memory device.

Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.

Abstract: Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.

Abstract: Over a period of operation, non-volatile memory can develop a residual resistance that is impractical to remove. For example, in a NAND string of memory cells, trapped charge may build up in a region between the bit lines and drain side select gates, so that even when all the devices of a NAND string are in an “on” state, the NAND string will not conduct. This effect will skew both hard bit data determinations, indicating the data state of a selected memory cell, and soft bit data determinations which may correlate to the reliability of the hard bit data. Techniques are described to factor in such excessive residual resistance when determining the soft bit data.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing a group read refresh. An apparatus includes a plurality of memory groups. An apparatus includes an operation circuit that performs an operation on a selected memory group of a plurality of memory groups. An apparatus includes a remediation circuit that performs a countermeasure operation on an unselected memory group of a plurality of memory groups in response to an operation on a selected memory group.

Abstract: Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.

Abstract: Blocks of memory cells may be selected for use based on one or more measured performance characteristics that may include, but are not limited to, programming time or fail bit count. Blocks may be placed into a single level cell (SLC) block pool and one or more multi-level cell (MLC) block pools based on measured performance characteristic(s). For example, blocks that have a better SLC performance may be placed into the SLC block pool. Blocks may be targeted for garbage collection based on one or more measured performance characteristics. For example, blocks within an SLC block pool may be targeted for garbage collection based on a performance ranking of the SLC blocks, blocks within an MLC block pool may be targeted for garbage collection based on a performance ranking of the MLC blocks. Thus, the better performing blocks may be used more frequently, thereby improving performance.