Abstract: A method may be performed in a data storage device that includes a memory including a three-dimensional (3D) memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.

Abstract: A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.

Abstract: In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations.

Abstract: A method performed in a data storage device including a non-volatile memory includes reading a representation of data, the representation corresponding to one or more selected states of storage elements of a group of storage elements of the non-volatile memory. The method includes, in response to a count of errors in the representation of the data exceeding a threshold, scheduling a remedial action to be performed on the group of storage elements.

Abstract: A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.

Abstract: A method includes reading a representation of tracking data from at least a portion of a non-volatile memory. The method further includes adjusting a read voltage based on a comparison between a number of bits in tracking data as compared to a count of bits in the representation of the tracking data.

Abstract: Disclosed is a technology to change the parameters by which a read operation is performed in a block with a broken word line. The first method is for reading a broken word line, which may involve changing the voltage on word lines neighboring the broken word line to let the voltage on the broken word line reach the appropriate magnitude through capacitive coupling between word lines. The first method may also involve increasing the time delay before memory cells connected to the broken word line are sensed to allow the voltage on the word line to settle due to increased RC delay. The second method is for reading an unbroken word line in a block with a broken word line, which involves increasing the time delay before memory cells connected to the unbroken word line are sensed while raising the voltages on the word lines neighboring the broken word line.

Abstract: A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states as SLC states in a first SLC mode, according to predefined sets of criteria. Subsequently, different MLC memory cell states are assigned as SLC states in a second SLC mode.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.

Abstract: A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.

Abstract: A data storage device includes a controller that is configured to determine a first read voltage for a first page of a non-volatile memory (e.g., a lower page of a Multi-Level Cell flash memory device). The controller is also configured to determine a second read voltage for a second page (e.g., an upper page) of the non-volatile memory by applying an offset value to the first read voltage. The controller is also configured to store data identifying the first read voltage and the second read voltage.

Abstract: Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.

Abstract: A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated.

Abstract: Disclosed is a technology to change the parameters by which a read operation is performed in a block with a broken word line. The first method is for reading a broken word line, which may involve changing the voltage on word lines neighboring the broken word line to let the voltage on the broken word line reach the appropriate magnitude through capacitive coupling between word lines. The first method may also involve increasing the time delay before memory cells connected to the broken word line are sensed to allow the voltage on the word line to settle due to increased RC delay. The second method is for reading an unbroken word line in a block with a broken word line, which involves increasing the time delay before memory cells connected to the unbroken word line are sensed while raising the voltages on the word lines neighboring the broken word line.

Abstract: A nonvolatile memory recycles previously written blocks by reassigning binary logic states and further programming memory cells with modified parameters. Cells are written twice between erase operations, thus reducing wear, and providing higher endurance. Flags indicate whether blocks are recycled, and what parameters to use in programming and reading the blocks.

Abstract: Charge leakage from a floating gate in a NAND flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die.

Abstract: In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations.

Abstract: A nonvolatile memory recycles previously written blocks by reassigning binary logic states and further programming memory cells with modified parameters. Cells are written twice between erase operations, thus reducing wear, and providing higher endurance. Flags indicate whether blocks are recycled, and what parameters to use in programming and reading the blocks.

Abstract: A method may be performed in a data storage device that includes a memory including a three-dimensional (3D) memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.

Abstract: A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.