Patents by Inventor Nian Niles Yang

Nian Niles Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INSPECTION OF NON-VOLATILE MEMORY FOR DISTURB EFFECTS
    Publication number: 20140173382
    Abstract: A method performed in a data storage device including a non-volatile memory includes reading a representation of data, the representation corresponding to one or more selected states of storage elements of a group of storage elements of the non-volatile memory. The method includes, in response to a count of errors in the representation of the data exceeding a threshold, scheduling a remedial action to be performed on the group of storage elements.
    Type: Application
    Filed: February 2, 2013
    Publication date: June 19, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: NIAN NILES YANG, CHRIS AVILA, STEVEN SPROUSE, JIANMIN HUANG, YICHAO HUANG, KULACHET TANPAIROJ
  • SYSTEM AND METHOD TO UPDATE READ VOLTAGES IN A NON-VOLATILE MEMORY IN RESPONSE TO TRACKING DATA
    Publication number: 20140173172
    Abstract: A method includes reading a representation of tracking data from at least a portion of a non-volatile memory. The method further includes adjusting a read voltage based on a comparison between a number of bits in tracking data as compared to a count of bits in the representation of the tracking data.
    Type: Application
    Filed: February 2, 2013
    Publication date: June 19, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: NIAN NILES YANG, RYAN TAKAFUJI, SEUNGJUNE JEON, CHRIS AVILA, STEVEN SPROUSE
  • Adaptive Operation of Multi Level Cell Memory
    Publication number: 20140160842
    Abstract: A Multi Level Cell (MLC) nonvolatile memory is tested and, if it fails to meet an MLC specification, is reconfigured for operation as an SLC memory by assigning two of the MLC memory cell states as SLC states in a first SLC mode, according to predefined sets of criteria. Subsequently, different MLC memory cell states are assigned as SLC states in a second SLC mode.
    Type: Application
    Filed: January 14, 2013
    Publication date: June 12, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Ryan Chiezo Takafuji, Nian Niles Yang, Chris Nga Yee Avila
  • Flash Memory with Data Retention Bias
    Publication number: 20140126292
    Abstract: Charge leakage from a floating gate in a NAND flash memory die is reduced by applying a data retention bias to a word line extending over the floating gates. The data retention bias is applied to one or more selected word lines when the memory die is in idle mode, when no read, write, erase, or other commands are being executed in the memory die.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Nian Niles Yang, Ryan Takafuji, Chris Nga Yee Avila
  • Flash Memory with Data Retention Partition
    Publication number: 20140115230
    Abstract: A NAND flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data.
    Type: Application
    Filed: October 23, 2012
    Publication date: April 24, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Nian Niles Yang, Chris Nga Yee Avila, Steven T. Sprouse