Abstract: Methods to form a three-dimensional semiconductor package comprising a customized ultra-bandwidth elements (CUBE) die coat shielding particles with an electrically insulating coating, disperse the coated shielding particles in a base material to form a mold structure; and position the mold structure proximate the three-dimensional semiconductor package to shield the package from radiation. Devices comprising: a three-dimensional semiconductor package; and a mold structure proximate the three-dimensional semiconductor package, the mold structure comprising: a base material; and shielding particles comprising an electrically insulating coating, wherein the shielding particles are dispersed in the base material.

Abstract: Aspects of a storage device, a host device, and a redundant array of independent disks (RAID) system including multiple storage devices and the host device are provided that provide power control and power loss handling. The host device and the storage devices in the RAID system may each include at least a memory, a controller coupled to the memory, and a power management circuit coupled to the memory and the controller. A storage device controller may receive rationed power from the host device or a RAID controller in the host device in response to a message from that storage device indicating a detected loss in supplied power. An amount of the rationed power is based on a program data rate of the storage device or a size of data from the host device or the RAID controller to be written to the memory. Thus, UGSDs may be detected and addressed.

Abstract: Aspects of a storage device, a host device, and a redundant array of independent disks (RAID) system including multiple storage devices and the host device are provided that provide power control and power loss handling. The host device and the storage devices in the RAID system may each include at least a memory, a controller coupled to the memory, and a power management circuit coupled to the memory and the controller. A storage device controller may receive rationed power from the host device or a RAID controller in the host device in response to a message from that storage device indicating a detected loss in supplied power. An amount of the rationed power is based on a program data rate of the storage device or a size of data from the host device or the RAID controller to be written to the memory. Thus, UGSDs may be detected and addressed.

Abstract: Aspects of a storage device are provided that provide power control and power loss handling in a RAID system. The storage device may include a memory, a controller coupled to the memory, a power management circuit coupled to the memory and the controller, and a rechargeable battery coupled to the power management circuit. The controller may receive power supplied by a RAID controller, receive a notification of a loss in power supplied to another storage device, and cause the power management circuit to detect a charge of the rechargeable battery in response to the notification. The power management circuit may also detect another loss in power supplied by the RAID controller, cause the controller to send a message to the RAID controller indicating the loss in power, and receive power from the RAID controller in response to the message. As a result, UGSDs in RAID may be detected and addressed.

Abstract: Aspects of a storage device are provided that provide power control and power loss handling in a RAID system. The storage device may include a memory, a controller coupled to the memory, a power management circuit coupled to the memory and the controller, and a rechargeable battery coupled to the power management circuit. The controller may receive power supplied by a RAID controller, receive a notification of a loss in power supplied to another storage device, and cause the power management circuit to detect a charge of the rechargeable battery in response to the notification. The power management circuit may also detect another loss in power supplied by the RAID controller, cause the controller to send a message to the RAID controller indicating the loss in power, and receive power from the RAID controller in response to the message. As a result, UGSDs in RAID may be detected and addressed.

Abstract: A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.

Abstract: A method and apparatus for dynamically determining when, or how often, to do a read scan operation on a solid-state storage drive. One solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Then, a cross temperature metric for the storage block is determined. A read scan interval is changed in response to the cross temperature metric satisfying a cross temperature threshold. Then, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.

Abstract: A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.

Abstract: A method and apparatus for dynamically determining when, or how often, to do a read scan operation on a solid-state storage drive. One solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Then, a cross temperature metric for the storage block is determined. A read scan interval is changed in response to the cross temperature metric satisfying a cross temperature threshold. Then, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.

Abstract: A circuit configured to dynamically adjust data transfer speeds for a non-volatile memory die interface. The circuit includes an initialization circuit, a control circuit, a switch circuit, and a read-write circuit. The initialization circuit is configured to load multi-level cell settings that configure a memory interface for transfer of data for storage cells configured to store more than one bit per storage cell. The control circuit is configured to receive a read command that references single-level storage cells of a memory die. The switch circuit is configured to switch settings for the memory interface from the multi-level cell settings to single level cell settings, in response to receiving the read command. The read-write circuit is configured to read data for the read command from the memory die using the single level cell settings.

Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.

Abstract: A method includes determining a first taxonomy of an anchor product. The first taxonomy includes a plurality of levels for classifying products organized from a highest taxonomy level to a lowest taxonomy level. The method further includes determining a second taxonomy closest to the first taxonomy. The second taxonomy is associated with a group of products, the first taxonomy and the second taxonomy have at least a common highest taxonomy level, and the determination is made at least in part based on co-purchase data indicating that the anchor product and at least one product in the group of products are purchased together more often than products associated with other taxonomies are purchased with the anchor product. The method further includes determining a most similar product to the anchor product from the group of products of the second taxonomy and associating the anchor product and the most similar product with one another in a product collection.

Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.

Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.

Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.

Abstract: The present application provides a method and system for detecting malicious web addresses. The method includes: receiving a uniform resource locator (URL) reported by a user; acquiring a HyperText Transfer Protocol (HTTP) request chain associated with the URL, wherein the HTTP request chain is a sequential linked list including information about multiple HTTP request-response interactions during an access to the URL; and analyzing the HTTP request chain to determine whether the URL is a malicious web address. The technical solution of the present application can provide an accurate result of malicious web address detection, can detect various newly emerging malicious web addresses, and are user-friendly. The user only needs to upload the URL and does not need to provide any other information.

Abstract: The present disclosure provides a method and system for detecting a phishing page. The method comprises: intercepting user data attempted to be submitted by a current page to a server; constructing detection data having a structure identical to a structure of the user data, content of the detection data being different from content of the user data; submitting the detection data to the server; and determining whether the current page is a phishing page based on a response from the server. By using the method and the system for detecting a phishing page provided in the present disclosure, a user can immediately and accurately determine whether the current page is a phishing page, thereby protecting privacies and assets better.

Abstract: The present disclosure provides a method and system for detecting a phishing page. The method comprises: intercepting user data attempted to be submitted by a current page to a server; constructing detection data having a structure identical to a structure of the user data, content of the detection data being different from content of the user data; submitting the detection data to the server; and determining whether the current page is a phishing page based on a response from the server. By using the method and the system for detecting a phishing page provided in the present disclosure, a user can immediately and accurately determine whether the current page is a phishing page, thereby protecting privacies and assets better.

Abstract: The present application provides a method and system for detecting malicious web addresses. The method includes: receiving a uniform resource locator (URL) reported by a user; acquiring a HyperText Transfer Protocol (HTTP) request chain associated with the URL, wherein the HTTP request chain is a sequential linked list including information about multiple HTTP request-response interactions during an access to the URL; and analyzing the HTTP request chain to determine whether the URL is a malicious web address. The technical solution of the present application can provide an accurate result of malicious web address detection, can detect various newly emerging malicious web addresses, and are user-friendly. The user only needs to upload the URL and does not need to provide any other information.

Abstract: Apparatus and methods implemented therein use an ECC procedure to verify and correct errors in data corresponding to pre-programmed configuration data. Verification and correction is performed in a memory system comprising a non-volatile memory (NVM) and a read only memory (ROM). The NVM comprises a plurality of memory pages. On detecting a power-on reset (POR) command at the memory system, a determination is made whether the memory system has previously received the POR command from a host. When it is determined that the memory system has not previously received the POR command from the host, pre-programmed configuration data is read from the ROM and the memory system is initialized using the pre-programmed configuration data. An error correction code (ECC) is generated for the pre-programmed configuration data and the pre-programmed configuration data including the ECC is store in one of the plurality of pages of the NVM memory.