Abstract: Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.

Abstract: A method of forming a capacitor for use as a charge pump with flash memory, comprising: (a) concurrently forming polysilicon gates on a semiconductor body in a core region and a polysilicon middle capacitor plate in a peripheral region, (b) forming a first dielectric layer over the polysilicon gates and the middle capacitor plate, (c) planarizing the first dielectric layer to expose a top portion of the polysilicon gates and a top portion of the middle capacitor plate, (d) forming a second dielectric layer over the top portion of the middle capacitor layer, (e) concurrently forming patterning a second polysilicon layer in the core region and a third capacitor plate in the periphery region and (f) connecting the third capacitor plate to the source/drain well.

Abstract: Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell.

Abstract: A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.

Abstract: Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

Abstract: A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period.

Abstract: One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell. Other methods and systems are also disclosed.

Abstract: A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.

Abstract: A fast reference circuit having active feedback includes a bias supply circuit and a variable divider circuit connected by an active feedback path to the bias supply circuit, and a comparator circuit connected to the variable divider circuit, the bias supply circuit, and a reference node of the variable divider circuit. In one embodiment, a start-up circuit initially discharges a potential at the bias supply and comparator circuits, then initializes a reference voltage at the reference node at about zero volts to improve repeatability. In one embodiment, the variable voltage divider comprises an impendence that is trimmed based on a sheet resistance of a process used to fabricate the fast reference circuit, and further comprises a variable reference current circuit coupled to the impedance and configured to generate a current having a value based on a desired reference voltage and to conduct the current through the impedance, thereby generating the reference voltage associated therewith.

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).

Abstract: A method and apparatus are provided for versatile high voltage level detection. A semiconductor device (100) is provided which includes a high voltage generating circuit (202) for generating a high voltage supply signal having a high voltage level and a voltage level detector (204) coupled to the output of the high voltage generating circuit (202) and including a current source (402) for generating a current to increase the voltage margin of the voltage level detector (204), the voltage level detector (204) generating a voltage control signal in response to the current and the high voltage level detected.

Abstract: A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pumps (202) is staggered (304, 310). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups (204) of drain pumps (202) are switched on and off in response to various predetermined high voltage levels (410, 412, 414, 416), with different voltage levels for different groups (204) of drain pumps (202).

Abstract: A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).

Abstract: A method and apparatus are provided for improved power conservation in a semiconductor device (100) which includes a high voltage generating circuit (200) such as a drain pump. The operation frequency of the drain pump (200) is controlled in response to the high voltage level detected at the output thereof. In addition, highly efficient operation of the drain pump (200) can be achieved by enabling and disabling the drain pump (200) in response to the high voltage level to provide an output signal at a relatively constant high voltage level. The drain pump (200) is enabled in response to a high voltage detector (202, 402, 502) detecting a high voltage level lower than a first predetermined voltage level and is disabled in response to detecting a voltage level higher than a second predetermined voltage level, the second predetermined voltage level being higher than the first predetermined voltage level.

Abstract: A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pumps (202) is staggered (304, 310). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups (204) of drain pumps (202) are switched on and off in response to various predetermined high voltage levels (410, 412, 414, 416), with different voltage levels for different groups (204) of drain pumps (202).

Abstract: According to one exemplary embodiment, a memory array includes a number of bitlines. The memory array further includes a voltage supply circuit, where the voltage supply circuit is configured to receive an operating voltage and a control signal and to output a low output voltage in a switching mode and a high output voltage in a programming mode. The low output voltage can be approximately equal to the operating voltage in the switching mode. In the programming mode, the high output voltage is greater than the operating voltage. According to this exemplary embodiment, the voltage supply circuit is in the programming mode when one of the bitlines is selected for programming. The voltage supply circuit is in the switching mode if none of the bitlines is selected for programming. The high output voltage can cause a bitline programming voltage to be applied to a selected bitline in the programming mode.