Abstract: An optical neural network is constructed based on photonic integrated circuits to perform neuromorphic computing. In the optical neural network, matrix multiplication is implemented using one or more optical interference units, which can apply an arbitrary weighting matrix multiplication to an array of input optical signals. Nonlinear activation is realized by an optical nonlinearity unit, which can be based on nonlinear optical effects, such as saturable absorption. These calculations are implemented optically, thereby resulting in high calculation speeds and low power consumption in the optical neural network.

Abstract: Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.

Abstract: Systems and methods for designing a chip configured to perform computing processes are provided. The described techniques include obtaining information associated with the chip and determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip. The chip architecture may then be generated to be used in fabrication of the chip based on the selections of the one or more circuit building blocks.

Abstract: Electronic-photonic packages and related fabrication methods are described. A package may include a plurality of photonic integrated circuits (PICs), where each PIC comprises a photonic accelerator configured to perform matrix multiplication in the optical domain. The package may further include an application specific integrated circuit (ASIC) configured to control at least one of the photonic accelerators. The package further includes an interposer. The plurality of PICs are coupled to a first side of the interposer and the ASIC is coupled to a second side of the interposer opposite the first side. A first thermally conductive member in thermal contact with at least one of the PICs. The first thermally conductive member may include a heat spreader. A second thermally conductive member in thermal contact with the ASIC. The second thermally conductive member may include a lid.

Abstract: Methods and apparatus for training a matrix-based differentiable program using a photonics-based processor. The matrix-based differentiable program includes at least one matrix-valued variable associated with a matrix of values in a Euclidean vector space. The method comprises configuring components of the photonics-based processor to represent the matrix of values as an angular representation, processing, using the components of the photonics-based processor, training data to compute an error vector, determining in parallel, at least some gradients of parameters of the angular representation, wherein the determining is based on the error vector and a current input training vector, and updating the matrix of values by updating the angular representation based on the determined gradients.

Abstract: Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.

Abstract: Methods and apparatus for training a matrix-based differentiable program using a photonics-based processor. The matrix-based differentiable program includes at least one matrix-valued variable associated with a matrix of values in a Euclidean vector space. The method comprises configuring components of the photonics-based processor to represent the matrix of values as an angular representation, processing, using the components of the photonics-based processor, training data to compute an error vector, determining in parallel, at least some gradients of parameters of the angular representation, wherein the determining is based on the error vector and a current input training vector, and updating the matrix of values by updating the angular representation based on the determined gradients.

Abstract: Methods and apparatus for tuning a photonics-based component. An opto-electrical detector is configured to output an electrical signal based on a measurement of light intensity of the photonics-based component, the light intensity being proportional to an amount of detuning of the photonics-based component. Analog-to-digital conversion (ADC) circuitry is configured to output a digital signal based on the electrical signal output from the opto-electrical detector. Feedback control circuitry is configured to tune the photonics-based component based, at least in part, on the digital signal output from the ADC circuitry.

Abstract: Methods and apparatus for tuning a photonics-based component. An opto-electrical detector is configured to output an electrical signal based on a measurement of light intensity of the photonics-based component, the light intensity being proportional to an amount of detuning of the photonics-based component. Analog-to-digital conversion (ADC) circuitry is configured to output a digital signal based on the electrical signal output from the opto-electrical detector. Feedback control circuitry is configured to tune the photonics-based component based, at least in part, on the digital signal output from the ADC circuitry.

Abstract: Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.

Abstract: A photonic processor uses light signals and a residue number system (RNS) to perform calculations. The processor sums two or more values by shifting the phase of a light signal with phase shifters and reading out the summed phase with a coherent detector. Because phase winds back every 2? radians, the photonic processor performs addition modulo 2?. A photonic processor may use the summation of phases to perform dot products and correct erroneous residues. A photonic processor may use the RNS in combination with a positional number system (PNS) to extend the numerical range of the photonic processor, which may be used to accelerate homomorphic encryption (HE)-based deep learning.

Abstract: A memory device is described. The memory device comprises a plurality of stacked memory layers, wherein each of the plurality of stacked memory layers comprises a plurality of memory cells. The memory device further comprises an optical die bonded to the plurality of stacked memory layers and in electrical communication with the stacked memory layers through one or more interconnects. The optical die comprises an optical transceiver, and a memory controller configured to control read and/or write operations of the stacked memory layers. The optical die may be positioned at one end of the plurality of stacked memory layers. The one or more interconnects may comprise one or more through silicon vias (TSV). The plurality of memory cells may comprise a plurality of solid state memory cells. The memory devices described herein can enable all-to-all, point-to-multipoint and ring architectures for connecting logic units with memory devices.

Abstract: Described herein are techniques of training a machine learning model and performing inference using an analog processor. Some embodiments mitigate the loss in performance of a machine learning model resulting from a lower precision of an analog processor by using an adaptive block floating-point representation of numbers for the analog processor. Some embodiments mitigate the loss in performance of a machine learning model due to noise that is present when using an analog processor. The techniques involve training the machine learning model such that it is robust to noise.

Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.

Abstract: Low-noise optical differential receivers are described. Such differential receivers may include a differential amplifier having first and second inputs and first and second outputs, and four photodetectors. A first and a second of such photodetectors are coupled to the first input of the differential amplifier, and a third and a fourth of such photodetectors are coupled to the second input of the differential amplifier. The anode of the first photodetector and the cathode of the second photodetector are coupled to the first input of the differential amplifier. The cathode of the third photodetector and the anode of the fourth photodetector are coupled to the second input of the differential amplifier. The optical receiver may involve two stages of signal subtraction, which may significantly increase noise immunity.

Abstract: Photonic packages are described. One such photonic package includes a photonic chip, an application specific integrated circuit, and optionally, an interposer. The photonic chip includes photonic microelectromechanical system (MEMS) devices. A photonic package may include a material layer patterned to include recesses. The recesses are aligned with the photonic MEMS devices so as to form enclosed cavities around the photonic MEMS devices. This arrangement preserves the integrity of the photonic MEMS devices.

Abstract: Typically, quantum systems are very sensitive to environmental fluctuations, and diagnosing errors via measurements causes unavoidable perturbations. Here, an in situ frequency-locking technique monitors and corrects frequency variations in single-photon sources based on resonators. By using the classical laser fields used for photon generation as probes to diagnose variations in the resonator frequency, the system applies feedback control to correct photon frequency errors in parallel to the optical quantum computation without disturbing the physical qubit. Our technique can be implemented on a silicon photonic device and with sub 1 pm frequency stabilization in the presence of applied environmental noise, corresponding to a fractional frequency drift of <1% of a photon linewidth. These methods can be used for feedback-controlled quantum state engineering.

Abstract: Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.

Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.

Abstract: Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.