Abstract: A photonic processor uses light signals and a residue number system (RNS) to perform calculations. The processor sums two or more values by shifting the phase of a light signal with phase shifters and reading out the summed phase with a coherent detector. Because phase winds back every 2? radians, the photonic processor performs addition modulo 2?. A photonic processor may use the summation of phases to perform dot products and correct erroneous residues. A photonic processor may use the RNS in combination with a positional number system (PNS) to extend the numerical range of the photonic processor, which may be used to accelerate homomorphic encryption (HE)-based deep learning.

Abstract: A memory device is described. The memory device comprises a plurality of stacked memory layers, wherein each of the plurality of stacked memory layers comprises a plurality of memory cells. The memory device further comprises an optical die bonded to the plurality of stacked memory layers and in electrical communication with the stacked memory layers through one or more interconnects. The optical die comprises an optical transceiver, and a memory controller configured to control read and/or write operations of the stacked memory layers. The optical die may be positioned at one end of the plurality of stacked memory layers. The one or more interconnects may comprise one or more through silicon vias (TSV). The plurality of memory cells may comprise a plurality of solid state memory cells. The memory devices described herein can enable all-to-all, point-to-multipoint and ring architectures for connecting logic units with memory devices.

Abstract: Described herein are techniques of training a machine learning model and performing inference using an analog processor. Some embodiments mitigate the loss in performance of a machine learning model resulting from a lower precision of an analog processor by using an adaptive block floating-point representation of numbers for the analog processor. Some embodiments mitigate the loss in performance of a machine learning model due to noise that is present when using an analog processor. The techniques involve training the machine learning model such that it is robust to noise.

Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.

Abstract: Low-noise optical differential receivers are described. Such differential receivers may include a differential amplifier having first and second inputs and first and second outputs, and four photodetectors. A first and a second of such photodetectors are coupled to the first input of the differential amplifier, and a third and a fourth of such photodetectors are coupled to the second input of the differential amplifier. The anode of the first photodetector and the cathode of the second photodetector are coupled to the first input of the differential amplifier. The cathode of the third photodetector and the anode of the fourth photodetector are coupled to the second input of the differential amplifier. The optical receiver may involve two stages of signal subtraction, which may significantly increase noise immunity.

Abstract: Photonic packages are described. One such photonic package includes a photonic chip, an application specific integrated circuit, and optionally, an interposer. The photonic chip includes photonic microelectromechanical system (MEMS) devices. A photonic package may include a material layer patterned to include recesses. The recesses are aligned with the photonic MEMS devices so as to form enclosed cavities around the photonic MEMS devices. This arrangement preserves the integrity of the photonic MEMS devices.

Abstract: Typically, quantum systems are very sensitive to environmental fluctuations, and diagnosing errors via measurements causes unavoidable perturbations. Here, an in situ frequency-locking technique monitors and corrects frequency variations in single-photon sources based on resonators. By using the classical laser fields used for photon generation as probes to diagnose variations in the resonator frequency, the system applies feedback control to correct photon frequency errors in parallel to the optical quantum computation without disturbing the physical qubit. Our technique can be implemented on a silicon photonic device and with sub 1 pm frequency stabilization in the presence of applied environmental noise, corresponding to a fractional frequency drift of <1% of a photon linewidth. These methods can be used for feedback-controlled quantum state engineering.

Abstract: Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.

Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.

Abstract: Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.

Abstract: Low-noise optical differential receivers are described. Such differential receivers may include a differential amplifier having first and second inputs and first and second outputs, and four photodetectors. A first and a second of such photodetectors are coupled to the first input of the differential amplifier, and a third and a fourth of such photodetectors are coupled to the second input of the differential amplifier. The anode of the first photodetector and the cathode of the second photodetector are coupled to the first input of the differential amplifier. The cathode of the third photodetector and the anode of the fourth photodetector are coupled to the second input of the differential amplifier. The optical receiver may involve two stages of signal subtraction, which may significantly increase noise immunity.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix multiplications (e.g., matrix vector multiplications). Matrix multiplications are broken down in scalar multiplications and scalar additions. Some embodiments relate to devices for performing scalar additions in the optical domain. One optical adder, for example, includes an interferometer having a plurality of phase shifters and a coherent detector. Leveraging the high-speed characteristics of these optical adders, some processors are sufficiently fast to support clocks in the tens of gigahertz of frequency, which represent a significant improvement over conventional electronic processors.

Abstract: Optical chips and packages are described. The optical chips and packages described herein are configured to output high-power, single mode optical outputs for use by integrated photonics packages. Some embodiments relate to an optical chip or package including a light source array configured to output a plurality of first optical signals and an optical combiner configured to receive the plurality of first optical signals from the light source array and to output a second optical signal that is a combination of the received plurality of first optical signals. The optical combiner may include at least one tunable element configured to increase an optical power of the output second optical signal.

Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.

Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.

Abstract: Described herein are photonic communication platforms and related packages. In one example, a photonic package includes a substrate carrier having a recess formed through the top surface of the substrate carrier. The substrate carrier may be made of a ceramic laminate. A photonic substrate including a plurality of photonic modules is disposed in the recess. The photonic modules may be patterned using a common photomask, and as a result, may share a same layer pattern. A plurality of electronic dies may be positioned on top of respective photonic modules. The photonic modules enable communication among the dies in the optical domain. Power delivery substrates may be used to convey electric power from the substrate carrier to the electronic dies and to the photonic substrate. Power delivery substrates may be implemented, for example, using bridge dies or interposers (e.g., silicon or organic interposers).

Abstract: Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.