Abstract: A D-type, master/slave, flip-flop is described for use as a divide-by-2 frequency divider in which a frequency to be divided is input as a clock signal and the Q output is connected to the D input, and in which the master section and the slave section consist only of tracking means, latching being effected by using potentials established on tracking transistors of each section during the previous clock pulse.

Abstract: A modulator circuit comprises an input for receiving an audio frequency (AF) signal, an oscillator circuit for providing a carrier wave signal, a mixer circuit for mixing the AF input signal with the carrier wave signal to provide an AM modulated signal, a switch having a first position in which the AM modulated signal is provided to an output and the switch having a second position in which the AM modulated signal is provided to a vector adding circuit where the AM modulated signal is vector added to the carrier wave signal, and the circuit including phase shift circuitry for shifting the phase of the AM modulated signal prior to vector adding with the carrier wave signal whereby to provide an FM modulated version of the AF input signal on the oscillator carrier wave.

Abstract: A frequency synthesizer phase locked loop includes a voltage controlled oscillator (VCO) providing a variable frequency signal, a reference frequency oscillator providing a reference frequency signal, a phase comparison circuit for comparing the phases of the variable frequency and reference frequency signals and providing an output signal to a loop filter, the output of the loop filter providing a frequency control signal to the VCO. The phase comparison circuit includes a digital phase detector providing an output signal on an output line coupled to a charge pump for providing a first output signal to the loop filter; and an analog phase detector including a sample and hold circuit, and a control circuit responsive to the variable and reference frequency signals for providing a signal for sampling to the sample and hold circuit, the sample and hold circuit providing a second output signal to the loop filter.

Abstract: An oscillator is provided with an internal, high gain hysteresis effect so as to offset the linear regions of the waveform and to avoid spikes upsetting the count of a reference divider controlling the oscillator. The crystal (10) and capacitor (11) are connected between the base of one (T.sub.1) and the collector of the other (T.sub.2) transistor of a long-tailed pair, signals appearing at the collector thereof being fed via emitter followers (T.sub.5, T.sub.6) to a further long-tailed pair (T.sub.7, T.sub.8) having tapped collector resistors (R.sub.1, R.sub.2). The signal appearing at the tapping point of one of the further pair (T.sub.7) is fed to the base of a transistor (T.sub.3) whose collector-emitter resistor lies in the load circuit of one of the transistors (T.sub.1) of the first long-tailed pair.

Abstract: An FM demodulator comprises an injection locked oscillator/divider for receiving an input signal to be demodulated. The injection locked oscillator/divider is coupled via a divider to a frequency discriminator, such as a quadrature demodulator, for providing a demodulated output signal. A feedback loop is provided to afford the demodulated output signal to a varactor tuning circuit of the injection locked oscillator/divider so that the center frequency of the injection locked oscillator/divider is constrained to correspond with the frequency of the input signal. The FM demodulator provides improved threshold extension and demodulated video bandwidth.

Abstract: A dividing mechanism for use in frequency synthesizers: comprising:a two modulus divider system having a first and second counter for providing respective programmable count totals A, M, and first counter being coupled to a dual modulus device providing moduli of n and n+1 whereby the two modulus divider system provides a division ratio of (Mn+A) for incoming signals:first and second input means for receiving first and second programming number signals N, Q, synchronization means for receiving a strobe signal from a further counter which provides a count total P, and logic interface means responsive to said first and second input means and said synchronization means to provide programming number signals A, M to said two modulus divider system, the logic interface means being such that in the absence of said strobe signal the two modulus divider system provides a count total C.sub.

Abstract: In the present invention a switchable synthesizer is disclosed wherein a single loop is used to lock any one of a plurality of control signals by multiplexing the frequencies into and control signals out of the specific frequencies loop to control the frequency generators.

Abstract: The frequency synthesizer has a store which temporarily stores a data word for controlling a processor. A local oscillator provides a signal for the processor which drives an output interface to produce the required frequency. The output interface and processor are controlled by a control and decode circuit which also controls a reference divider. The output of the reference divider is compared with an output from the processor by a phase comparator and the signal generated is used to control the local oscillator. The reference divider is driven by a single reference oscillator.

Abstract: A frequency dividing arrangement 5 comprises a frequency divider 6 coupled to an active filler 7 which is operative to suppress output radiation from the frequency dividing arrangement. The arrangement 5 may be incorporated into a frequency synthesis loop 4 of a television tuner circuit in order to reduce interference between the loop 4 and a down conversion stage of the tuner circuit.

Abstract: An oscillator of balanced design in which a resonant impedance network is connected between the control ports of two matched transistors, and a capacitance is connected in parallel, across the two inputs of these transistors. The inputs of the transistors are connected each to a matched current source. The signals at the transistor outputs are summed together at a common node. Signals of resonant frequency in each arm of the oscillator are equal in magnitude but opposite in phase. Signals at resonant frequency thus cancel whereas signals at the second harmonic frequency add constructively and are thus enhanced. The effect is a net frequency doubling. For high frequency operation, bipolar transistors are utilized. The current sources can be modulated and an IF mixer output derived. Signal of resonant frequency can be extracted and used for signal prescaling. In an equivalent arrangement, an inductance and resonant network replace the resonant network and capacitance just mentioned.

Abstract: A frequency dividing arrangement comprises an injection-locked divider arranged for receiving an incoming signal F.sub.in and for providing a frequency divided signal F.sub.out in response thereto, and a frequency divider coupled to the injection-locked divider. The frequency divider comprises logical circuits for providing a further frequency divided signalF".sub.out in response to the frequency divided signal F.sub.out provided by the injection-locked divider. The arrangement may be included in a frequency modulation receiver which comprises an FM detector. The injection-locked divider comprises a multiplier, and a tuning circuit.

Abstract: A lock detect circuit (FIG. 3) for use in a synthesiser of the type comprising a phase comparator (5), a reference frequency source (11, 13, 15) a variable frequency oscillator (1), a variable divider (3) and a loop amplifier (7). The circuit includes logic gates (31, 33, . . . 41) to monitor the frequency `up` and frequency `down` error signals (C.sub.U, C.sub.D) produced by the comparator (5) and provides an `in-lock` indication (S) when frequency `up` or frequency `down` signals exclusively are detected in a predetermined period ( .sub.D). Accordingly this circuit may comprise a variable delay (31) an inverter (33) an AND-gate (35) and an OR-gate (39) for generating a comparison signal:f'.sub.E =F.sub.N .multidot.C.sub.D +C.sub.Uwhere f.sub.N is the signal from the inverter time delay pair derived from the divider output. This signal is fed to a series of flip-flops (37) clocked by the frequency down signal.

Abstract: In a tuner circuit, the relatively high voltage used to control a varactor diode of the circuit is derived using a cascade of resistors and transistors under the control of a reference voltage input. The breakdown voltage of each transistor is significantly less than the output voltage of the cascade and is such that the cascade can be implimented in the same semiconductor chip as high frequency, low voltage process, synthesiser components.

Abstract: Apparatus for obtaining programmable threshold extension of an FM demodulator comprises a limiter preamplifier 4 and a variable gain buffer amplifier 6. The buffer amplifier 6 is provided with an external control node 16 such that the signal level fed from the buffer amplifier 6 to an injection locked oscillator/divider 8 can be programmed in dependence upon a control signal applied to the external control node 16. In this manner threshold extension of the FM demodulator can be selectively applied in dependence upon the noise level in an FM input signal to be demodulated. The limiter preamplifier 4 and the buffer amplifier 6 may form part of an automatic gain control circuit.