Patents by Inventor Nicholas Rizzo
Nicholas Rizzo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8518734Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a āZā axis magnetic field onto sensors orientated in the XY plane.Type: GrantFiled: March 31, 2010Date of Patent: August 27, 2013Assignee: Everspin Technologies, Inc.Inventors: Renu Whig, Phillip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
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Patent number: 8508221Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.Type: GrantFiled: August 30, 2010Date of Patent: August 13, 2013Assignee: Everspin Technologies, Inc.Inventors: Jijun Sun, Phillip Mather, Srinivas Pietambaram, Jon Slaughter, Renu Whig, Nicholas Rizzo
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Patent number: 8390283Abstract: Three bridge circuits (101, 111, 121), each include magnetoresistive sensors coupled as a Wheatstone bridge (100) to sense a magnetic field (160) in three orthogonal directions (110, 120, 130) that are set with a single pinning material deposition and bulk wafer setting procedure. One of the three bridge circuits (121) includes a first magnetoresistive sensor (141) comprising a first sensing element (122) disposed on a pinned layer (126), the first sensing element (122) having first and second edges and first and second sides, and a first flux guide (132) disposed non-parallel to the first side of the substrate and having an end that is proximate to the first edge and on the first side of the first sensing element (122). An optional second flux guide (136) may be disposed non-parallel to the first side of the substrate and having an end that is proximate to the second edge and the second side of the first sensing element (122).Type: GrantFiled: September 25, 2009Date of Patent: March 5, 2013Assignee: Everspin Technologies, Inc.Inventors: Phillip Mather, Jon Slaughter, Nicholas Rizzo
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Publication number: 20120313191Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic, layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Renu WHIG, Jon SLAUGHTER, Nicholas RIZZO, Jijun SUN, Frederick MANCOFF, Dimitri HOUSSAMEDDINE
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Publication number: 20120193736Abstract: A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout.Type: ApplicationFiled: August 16, 2011Publication date: August 2, 2012Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Phillip Mather, Jon Slaughter, Nicholas Rizzo
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Patent number: 8228715Abstract: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.Type: GrantFiled: May 28, 2010Date of Patent: July 24, 2012Assignee: Everspin Technologies, Inc.Inventors: Thomas Andre, Saied Tehrani, Jon Slaughter, Nicholas Rizzo
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Publication number: 20120049843Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.Type: ApplicationFiled: August 30, 2010Publication date: March 1, 2012Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Jijun SUN, Phillip MATHER, Srinivas PIETAMBARAM, Jon SLAUGHTER, Renu WHIG, Nicholas RIZZO
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Publication number: 20120015099Abstract: A method for depositing uniform and smooth ferromagnetic thin films with high deposition-induced microstructural anisotropy includes a magnetic material deposited in two or more static oblique deposition steps from opposed directions to form a free layer having a high kink Hk, a high energy barrier to thermal reversal, a low critical current in spin-torque switching embodiments, and improved resistance to diffusion of material from adjacent layers in the device. Nonmagnetic layers deposited by the static oblique deposition technique may be used as seed layers for a ferromagnetic free layer or to generate other types of anisotropy determined by the deposition-induced microstructural anisotropy. Additional magnetic or non-magnetic layers may be deposited by conventional methods adjacent to oblique layer to provide magnetic coupling control, reduction of surface roughness, and barriers to diffusion from additional adjacent layers in the device.Type: ApplicationFiled: July 15, 2010Publication date: January 19, 2012Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Jijun SUN, Jon SLAUGHTER, Nicholas RIZZO
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Publication number: 20110292714Abstract: An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.Type: ApplicationFiled: May 28, 2010Publication date: December 1, 2011Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Thomas ANDRE, Saied TEHRANI, Jon SLAUGHTER, Nicholas RIZZO
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Publication number: 20110244599Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a āZā axis magnetic field onto sensors orientated in the XY plane.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Renu WHIG, Phillip MATHER, Kenneth SMITH, Sanjeev AGGARWAL, Jon SLAUGHTER, Nicholas RIZZO
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Publication number: 20110074406Abstract: Three bridge circuits (101, 111, 121), each include magnetoresistive sensors coupled as a Wheatstone bridge (100) to sense a magnetic field (160) in three orthogonal directions (110, 120, 130) that are set with a single pinning material deposition and bulk wafer setting procedure. One of the three bridge circuits (121) includes a first magnetoresistive sensor (141) comprising a first sensing element (122) disposed on a pinned layer (126), the first sensing element (122) having first and second edges and first and second sides, and a first flux guide (132) disposed non-parallel to the first side of the substrate and having an end that is proximate to the first edge and on the first side of the first sensing element (122). An optional second flux guide (136) may be disposed non-parallel to the first side of the substrate and having an end that is proximate to the second edge and the second side of the first sensing element (122).Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Phillip MATHER, Jon SLAUGHTER, Nicholas RIZZO
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Patent number: 7333360Abstract: Methods and apparatus are provided for testing a magnetoresistive random access memory (MRAM). A magnetoresistive tunnel junction (MTJ) has a first terminal, a second terminal, and a third terminal. A source measuring unit is coupled to a first terminal of a MTJ to provide DC biasing. A current preamp has an input coupled to a third terminal of the MTJ for receiving current corresponding to a resistance of the MTJ. A pulse generator is AC coupled to the MTJ for programming the MTJ. A method of insitu testing a MTJ in a manufacturing environment uses a probe station coupled to the MTJ. A probe station couples to the MTJ. The MTJ is DC biased for generating a current corresponding to the logic level stored in the MTJ. A pulse for programming the MTJ is AC coupled to the MTJ.Type: GrantFiled: December 23, 2003Date of Patent: February 19, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Mark DeHerrera, Nicholas Rizzo
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Publication number: 20080017939Abstract: Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.Type: ApplicationFiled: October 4, 2007Publication date: January 24, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Nicholas Rizzo, Renu Dave, Jon Slaughter, Srinivas Pietambaram
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Publication number: 20070284683Abstract: Low power magnetoelectronic device structures and methods therefore are provided. The magnetoelectronic device structure (100, 150, 450, 451) comprises a programming line (104, 154, 156, 454, 456), a magnetoelectronic device (102, 152, 452) magnetically coupled to the programming line (104, 154, 156, 454, 456), and an enhanced permeability dielectric (EPD) material (106, 108, 110, 158, 160, 162, 458, 460, 462) disposed adjacent the magnetoelectronic device. The EPD material (106, 108, 110, 158, 160, 162, 458, 460, 462) comprises multiple composite layers (408) of magnetic nano-particles (406) embedded in a dielectric matrix (409). The composition of the composite layers is chosen to provide a predetermined permeability profile. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating the magnetoelectronic device (102, 152, 452) and depositing the programming line (104, 154, 156, 454, 456).Type: ApplicationFiled: April 25, 2007Publication date: December 13, 2007Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Srinivas Pietambaram, Nicholas Rizzo, Jon Slaughter
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Publication number: 20070236105Abstract: An oscillator includes at least one of: (i) a parallel array of resistors (420, 421, 422, 701, 801, 901, 902) or magnetoresistive contacts to a magnetoresistive film (120, 320); and (ii) a series array of resistors (620, 621, 702, 902) or magnetoresistive contacts to individualized areas of at least one magnetoresistive film.Type: ApplicationFiled: September 13, 2005Publication date: October 11, 2007Inventors: Frederick Mancoff, Bradley Engel, Nicholas Rizzo
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Publication number: 20070190669Abstract: A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.Type: ApplicationFiled: February 10, 2006Publication date: August 16, 2007Applicant: Freescale Semiconductor, Inc.Inventors: Mark Durlam, Gloria Kerszykowski, Nicholas Rizzo, Eric Salter, Loren Wise
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Publication number: 20070037299Abstract: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin?(Hsat??sat)?(Hsw+?sw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW??{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.Type: ApplicationFiled: October 16, 2006Publication date: February 15, 2007Inventors: Nicholas Rizzo, Renu Dave, Bradley Engel, Jason Janesky, JiJun Sun
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Publication number: 20060245242Abstract: A method is provided for testing magnetic bits (3, 104, 514) of an array. A train of first (702), second (704), and third (706) pulses is provided to a desired bit, the first and second pulses beginning at a substantially similar low field and increasing in similar amounts with respect to successive trains of the first, second, and third pulses, the third pulse having a current amplitude sufficient to toggle the magnetic bit. A representative count is recorded in response to switching of the bit. The above steps are repeated and a determination is made of the current amplitude required to write and toggle the bit.Type: ApplicationFiled: April 29, 2005Publication date: November 2, 2006Inventors: Nicholas Rizzo, Mark Deherrera, Jason Janesky
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Publication number: 20060186495Abstract: Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Inventors: Nicholas Rizzo, Renu Dave, Jon Slaughter, Srinivas Pietambaram
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Publication number: 20060108620Abstract: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin?(Hsat?N?sat)?(Hsw+N?sw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW??{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.Type: ApplicationFiled: November 24, 2004Publication date: May 25, 2006Inventors: Nicholas Rizzo, Renu Dave, Bradley Engel, Jason Janesky, JiJun Sun