Abstract: A process for evaluating acceptability of a digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the process comprising: generating a leading edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating a trailing edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating an accepted-rejected signal, functionally related to the width of the pulse.

Abstract: According to the present invention, a process for use with automatic test equipment ("ATE") for determining a propagation delay in a semiconductor circuit is provided. In one embodiment of the invention, the process comprises the steps of determining an expected delay time by interpolating a first simulation capacitance, a second simulation capacitance, and an ATE capacitance, with a first simulated delay time and a second simulated delay time, the simulated delay times corresponding to the first and second simulated capacitances respectively, testing the semiconductor circuit with the ATE to determine an ATE delay time, and comparing the ATE delay time with the expected delay time to determine whether the propagation delay is acceptable.