Patents by Inventor Nicolas Loubet

Nicolas Loubet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to induce strain in 3-D microfabricated structures
    Patent number: 10483393
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin
  • Dielectric isolation in gate-all-around devices
    Patent number: 10453736
    Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie
  • CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM
    Publication number: 20190304845
    Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventors: Nicolas LOUBET, Pierre MORIN, Yann MIGNOT
  • Method for making a semiconductor device with a compressive stressed channel
    Patent number: 10431683
    Abstract: A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a substrate and a layer of a first semiconductor, which is crystalline, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a nanowire stack, b) making a dummy gate and outer spacers, covering a part of the nanowire stack which is formed by portions of the nanowires, c) etching the nanowire stack such that only said part of the stack is preserved, d) removing the portion of the second semiconductor nanowire, e) depositing, in a space formed by this removal, a sacrificial material portion, f) making source and drain regions and inner spacers, g) removing the dummy gate and the sacrificial material portion, h) making a gate.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 1, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Forming nanosheet transistor using sacrificial spacer and inner spacers
    Patent number: 10424651
    Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Julien Frougier, Nicolas Loubet
  • METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
    Publication number: 20190279912
    Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • SUB-THERMAL SWITCHING SLOPE VERTICAL FIELD EFFECT TRANSISTOR WITH DUAL-GATE FEEDBACK LOOP MECHANISM
    Publication number: 20190259856
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: February 16, 2018
    Publication date: August 22, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • SUB-THERMAL SWITCHING SLOPE VERTICAL FIELD EFFECT TRANSISTOR WITH DUAL-GATE FEEDBACK LOOP MECHANISM
    Publication number: 20190259858
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: December 20, 2018
    Publication date: August 22, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • SUB-THERMAL SWITCHING SLOPE VERTICAL FIELD EFFECT TRANSISTOR WITH DUAL-GATE FEEDBACK LOOP MECHANISM
    Publication number: 20190259857
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Application
    Filed: December 20, 2018
    Publication date: August 22, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism
    Patent number: 10388760
    Abstract: Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Ruilong Xie, Steven Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini
  • Nanosheet field-effect transistors including a two-dimensional semiconducting material
    Patent number: 10388732
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A plurality of channel layers are arranged in a layer stack, and a source/drain region is connected with the plurality of channel layers. A gate structure includes a plurality of sections that respectively surround the plurality of channel layers. The plurality of channel layers contain a two-dimensional semiconducting material.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Nicolas Loubet, Kangguo Cheng, Juntao Li
  • STEEP-SWITCH FIELD EFFECT TRANSISTOR WITH INTEGRATED BI-STABLE RESISTIVE SYSTEM
    Publication number: 20190252465
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 15, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • STEEP-SWITCH FIELD EFFECT TRANSISTOR WITH INTEGRATED BI-STABLE RESISTIVE SYSTEM
    Publication number: 20190252507
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a plurality of source/drains disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a plurality of trenches, each trench extending to a corresponding one of the plurality of source/drains. A trench contact is formed in each of the trenches in contact with the corresponding source/drain. A recess is formed in a portion of each trench contact below a top surface of the cap. A bi-stable resistive system (BRS) material is deposited in each recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch for each of the corresponding source/drains.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 15, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • SELF-LIMITING AND CONFINING EPITAXIAL NUCLEATION
    Publication number: 20190252494
    Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Inventors: ROBIN HSIN KUO CHAO, KANGGUO CHENG, NICOLAS LOUBET
  • STEEP-SWITCH FIELD EFFECT TRANSISTOR WITH INTEGRATED BI-STABLE RESISTIVE SYSTEM
    Publication number: 20190252508
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Application
    Filed: April 2, 2019
    Publication date: August 15, 2019
    Applicant: International Business Machines Corporation
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • FORMING NANOSHEET TRANSISTOR USING SACRIFICIAL SPACER AND INNER SPACERS
    Publication number: 20190252516
    Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Julien Frougier, Nicolas Loubet
  • SELF-LIMITING AND CONFINING EPITAXIAL NUCLEATION
    Publication number: 20190252493
    Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Inventors: ROBIN HSIN KUO CHAO, KANGGUO CHENG, NICOLAS LOUBET
  • FORMING NANOSHEET TRANSISTOR USING SACRIFICIAL SPACER AND INNER SPACERS
    Publication number: 20190237559
    Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Julien Frougier, Nicolas Loubet
  • Wrap around contact using sacrificial mandrel
    Patent number: 10367077
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a plurality of unmerged fin structures each in contact with their own source/drain. The semiconductor structure further includes a contact layer formed on sidewalls and a top surface of each source/drain. The method includes at least the following operations. At least one mandrel layer is formed adjacent to at least one fin structure. The at least one fin structure and at least one source/drain is epitaxially grown in contact with the at least one fin structure and the at least one mandrel layer. The at least one mandrel layer is removed after the at least one source/drain has been epitaxially grown. At least one contact layer is formed in contact with sidewalls and a top surface of the at least one source/drain.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Nicolas Loubet, Adra Carr, Kangguo Cheng
  • Replacement metal gate and inner spacer formation in three dimensional structures using sacrificial silicon germanium
    Patent number: 10367061
    Abstract: A technique relates to a semiconductor device. Stacks are formed each of which including two or more nanosheets separated by a high-k dielectric material. The high-k dielectric material is formed on at least a center portion of the two or more nanosheets in the stacks. A lower spacer material is on a periphery of the two or more nanosheets, and an upper spacer material is on the lower spacer material such that the upper spacer material is above a top one of the two or more nano sheets. Source and drain regions are formed on sides of the stacks.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Nicolas Loubet