Patents by Inventor Nicolas Loubet

Nicolas Loubet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10340341
    Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet
  • Patent number: 10340195
    Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 2, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Publication number: 20190198614
    Abstract: A method of fabrication of a semiconductor device including the implementation of the following steps: fabrication of a stack including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, such that the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure intended to be made; and thermal treatment of the stack at a temperature which causes surface migration of atoms of the second semiconductor of the second portion towards at least one part of the first portion which exhibits at least one free surface and at which the nanostructure containing at least atoms of the second semiconductor is formed.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, International Business Machines Corporation
    Inventors: Shay REBOH, Kangguo CHENG, Remi COQUAND, Nicolas LOUBET
  • Publication number: 20190189802
    Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 20, 2019
    Inventors: Pierre Morin, Nicolas Loubet
  • Publication number: 20190189740
    Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 20, 2019
    Inventors: ROBIN HSIN KUO CHAO, KANGGUO CHENG, NICOLAS LOUBET
  • Patent number: 10319816
    Abstract: A fin field effect transistor includes a Si fin including a central portion between end portions of the fin, and a SiGe channel region disposed on the central portion of the fin. The SiGe channel region includes a facet free SiGe region having Ge atoms diffused into the Si fin and includes a same shape as the Si fin outside the central portion.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 11, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Hong He, Nicolas Loubet, Junli Wang
  • Publication number: 20190157422
    Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 23, 2019
    Applicants: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines Corporation
    Inventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND, Nicolas LOUBET
  • Patent number: 10283418
    Abstract: A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 7, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Hong He, James Kuss, Nicolas Loubet, Junli Wang
  • Patent number: 10276442
    Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A first field-effect transistor has a first source/drain region, and a second field-effect transistor has a second source/drain region. A first silicide layer is arranged to wrap around the first source/drain region, and a second silicide layer is arranged to wrap around the second source/drain region. The first silicide layer contains a first metal, and the second silicide layer contains a second metal different from the first metal.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Julien Frougier, Kangguo Cheng, Adra Carr, Nicolas Loubet
  • Patent number: 10262905
    Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Qing Liu, Nicolas Loubet, Scott Luning
  • Publication number: 20190109040
    Abstract: A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.
    Type: Application
    Filed: October 9, 2017
    Publication date: April 11, 2019
    Applicant: International Business Machines Corporation
    Inventors: ROBIN HSIN KUO CHAO, Kangguo Cheng, Nicolas Loubet, Pietro Montanini, Ruilong Xie
  • Patent number: 10256316
    Abstract: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng
  • Patent number: 10256341
    Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 9, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Nicolas Loubet
  • Publication number: 20190081155
    Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 14, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong XIE, Kangguo CHENG, Nicolas LOUBET, Xin MIAO, Pietro MONTANINI, John ZHANG, Haigou HUANG, Jianwei PENG, Sipeng GU, Hui ZANG, Yi QI, Xusheng WU
  • Publication number: 20190051744
    Abstract: Fabrication of a microelectronic device comprising a semiconductor structure provided with semiconductor bars positioned above one another, the method comprising the following steps: creating, on a substrate, a stacked structure comprising an alternation of first bars containing a first material and having a first critical dimension and second bars (142, 144, 146) containing a second material, the second material being a semiconductor, the second bars having a second critical dimension greater than the first critical dimension, then, surface doping protruding lateral portions (15) of the second bars before formation of a source and drain block on these portions.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 14, 2019
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Remi Coquand, Nicolas Loubet, Shay Reboh, Robin Chao
  • Patent number: 10205022
    Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: February 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 10204982
    Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Qing Liu, Nicolas Loubet
  • Patent number: 10199392
    Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 5, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Ronald K. Sampson, Nicolas Loubet
  • Publication number: 20190035913
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Application
    Filed: May 16, 2018
    Publication date: January 31, 2019
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20190035911
    Abstract: A substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate is received and a dummy gate is formed upon the nanosheet layers and the sacrificial layers. A portion of a subset of the set of sacrificial layers and a subset of the set of nanosheet layers is etched. A portion of a subset of the subset of sacrificial layers is etched to create divots within the sacrificial layers. A divot fill layer is deposited. The divot fill layer is etched to form an inner spacer between the nanosheet layers. A source/drain region is formed adjacent to the nanosheet layers and the divots. A remaining portion of the subset of the sacrificial layers is removed. The subset of the nanosheet layers is etched to a desired channel thickness producing faceted surfaces between the subset of nanosheet layers and the inner spacer.
    Type: Application
    Filed: July 25, 2017
    Publication date: January 31, 2019
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, NICOLAS LOUBET, Ruilong Xie, TENKO YAMASHITA, CHUN-CHEN YEH