Abstract: A method and system are provided for etching a layer to be etched in a plasma etching reactor, including: forming a reactive layer by injection of at least one reactive gas to form a reactive gas plasma, which forms, together with the layer to be etched, a reactive layer which goes into the layer to be etched during etching of said layer to be etched, wherein the reactive layer reaches a steady state thickness upon completion of a determined duration of said injection; said injection being interrupted before said determined duration has elapsed so that, upon completion of the forming of the reactive layer, the thickness of the reactive layer is smaller than said steady state thickness; and removing the reactive layer by injection of at least one inert gas to form an inert gas plasma, which makes it possible to remove only the reactive layer.

Abstract: The present invention relates to a method for manufacturing a semiconductor device by wet-process chemical etching, the device comprising at least one layer of silicon (Si) and at least one layer of silicon-germanium (SiGe) and at least one layer of photosensitive resin forming a mask partly covering the layer of silicon-germanium (SiGe) and leaving the layer of silicon-germanium uncovered in certain zones, characterized in that it comprises a step of preparation of an etching solution, having a pH between 3 and 6, from hydrofluoric acid (HF), hydrogen peroxide (H2O2), acetic acid (CH3COOH) and ammonia (NH4OH), and a step of stripping of the layer of silicon-germanium (SiGe) at least at the said zones by exposure to the said etching solution. The invention will be applicable for the manufacture of integrated circuits and more precisely of transistors. In particular, for optimization of CMOS transistors of the latest generation.

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract: A method for forming spacers of a transistor gate having an active layer surmounted by the gate, including forming a porous layer covering the gate and having a dielectric constant equal to or less than that of silicon oxide, forming a protective layer covering the porous layer and the gate, etching the protective layer anisotropically to preserve residual portions of the protective gate only at the flanks of the gate, forming a modified layer by penetration of ions within the porous layer anisotropically to modify the porous layer over its entire thickness above the gate and above the active layer and so as not to modify the entire thickness of the porous layer on the flanks of the gate, the latter being protected by protective spacers constituting porous spacers, and removing the modified layer by etching to leave the protective spacers in place.

Abstract: According to one embodiment, the invention relates to a method for the anisotropic etching of patterns in at least one layer to be etched through a hard mask comprising carbon in an inductive-coupling plasma etching reactor (ICP), the method being characterized in that the hard mask is made from boron doped with carbon (B:C), and in that, prior to the anisotropic etching of the patterns in said layer to be etched through the hard mask of carbon-doped boron (B:C), the following steps are performed: realization of an intermediate hard mask situated on a layer of carbon-doped boron intended to form the hard mask made from carbon-doped boron (B:C), etching of the layer of carbon-doped boron (B:C) through the intermediate hard mask in order to form the hard mask made from carbon-doped boron (B:C), the realization of the intermediate hard mask and the etching of the hard mask made from carbon-doped boron (B:C) being done in said inductive coupling plasma etching reactor (ICP).

Abstract: The invention relates to the field of production in thin coatings of electronic devices and/or MEMS and relates to an improved method for forming a pattern in a thin SiARC anti-reflective coating, comprising the doping by deposition of such SiARC coating covered with a resist pattern through a protective coating of the resist pattern, then etching the doped zones of the SiARC coating (FIG. 3c).

Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.

Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.

Abstract: Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.

Abstract: The invention relates to the field of production in thin coatings of electronic devices and/or MEMS and relates to an improved method for forming a pattern in a thin SiARC anti-reflective coating, comprising the doping by deposition of such SiARC coating covered with a resist pattern through a protective coating of the resist pattern, then etching the doped zones of the SiARC coating (FIG. 3c).

Abstract: According to one embodiment, the invention relates to a method for the anisotropic etching of patterns in at least one layer to be etched through a hard mask comprising carbon in an inductive-coupling plasma etching reactor (ICP), the method being characterized in that the hard mask is made from boron doped with carbon (B:C), and in that, prior to the anisotropic etching of the patterns in said layer to be etched through the hard mask of carbon-doped boron (B:C), the following steps are performed: realization of an intermediate hard mask situated on a layer of carbon-doped boron intended to form the hard mask made from carbon-doped boron (B:C), etching of the layer of carbon-doped boron (B:C) through the intermediate hard mask in order to form the hard mask made from carbon-doped boron (B:C), the realization of the intermediate hard mask and the etching of the hard mask made from carbon-doped boron (B:C) being done in said inductive coupling plasma etching reactor (ICP).

Abstract: The invention relates to a method for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, comprising a step of forming a layer of nitride covering the transistor gate, the method being characterized in that it comprises: after the step of forming the layer of nitride, at least one step of modifying the layer of nitride by implantation of light ions in the layer of nitride in order to form a modified layer of nitride, the step of modification being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate, the step of modifying the layer of nitride by implantation being performed using a plasma comprising the light ions; at least one step of removing the modified layer of nitride by means of a selective etching of the modified layer of nitride vis-à-vis said semiconductor material and vis-à-vis the non-modified layer of nitride

Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.

Abstract: The field effect device is formed on a substrate of semiconductor on insulator type provided with a support substrate separated from a semiconductor film by an electrically insulating layer. The source and drain electrodes are formed in the semiconductor film on each side of the gate electrode. The electrically insulating layer comprises a first area having a first electric capacitance value between the semiconductor film and the support substrate facing the gate electrode. The electrically insulating layer comprises second and third areas having a higher electric capacitance value than the first value between the semiconductor film and the support substrate facing the source and drain electrodes.

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.

Abstract: The field effect device is formed on a substrate of semiconductor on insulator type provided with a support substrate separated from a semiconductor film by an electrically insulating layer. The source and drain electrodes are formed in the semiconductor film on each side of the gate electrode. The electrically insulating layer comprises a first area having a first electric capacitance value between the semiconductor film and the support substrate facing the gate electrode. The electrically insulating layer comprises second and third areas having a higher electric capacitance value than the first value between the semiconductor film and the support substrate facing the source and drain electrodes.

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.