Abstract: Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench; and a gate metal disposed on the insulating material and extending into the trench.

Abstract: Disclosed herein are quantum dot devices with conductive liners, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base, a first fin extending from the base, a second fin extending from the base, a conductive material between the first fin and the second fin, and a dielectric material between the conductive material and the first fin.

Abstract: Techniques are provided herein to form semiconductor devices having backside contacts. Sacrificial plugs are formed first within a substrate at particular locations to align with source and drain regions during a later stage of processing. Another wafer is subsequently bonded to the surface of the substrate and is thinned to effectively transfer different material layers to the top surface of the substrate. One of the transferred layers acts as a seed layer for the growth of additional semiconductor material used to form semiconductor devices. The source and drain regions of the semiconductor devices are sufficiently aligned over the previously formed sacrificial plugs. A backside portion of the substrate may be removed to expose the sacrificial plugs from the backside. Removal of the plugs and replacement of the recesses left behind with conductive material forms the conductive backside contacts to the source or drain regions.

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.

Abstract: Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. In an example, an upper (e.g., n-channel) device and a lower (e.g., p-channel) device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where the upper device is located vertically above the lower device. According to some embodiments, an internal spacer structure extends between the nanoribbons of the upper device and the nanoribbons of the lower device along the vertical direction, where the spacer structure has a stepwise or an otherwise outwardly protruding profile as it extends between the nanoribbons of the upper device and the lower device. Accordingly, in one example, a gate structure formed around the nanoribbons of both the n-channel device and the p-channel device exhibits a greater width in the region between the nanoribbons of the n-channel device and the nanoribbons of the p-channel device.

Abstract: A quantum dot device is disclosed that includes a quantum well stack, a first and a second plunger gates above the quantum well stack, and a passive barrier element provided in a portion of the quantum well stack between the first and the second plunger gates. The passive barrier element may serve as means for localizing charge in the quantum dot device and may be used to replace charge localization control by means of a barrier gate. In general, a quantum dot device with a plurality of plunger gates provided over a given quantum well stack may include a respective passive barrier element between any, or all, of adjacent plunger gates in the manner as described for the first and second plunger gates.

Abstract: Gallium nitride (GaN) layer transfer for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A first layer including gallium and nitrogen is over a first region of the substrate, the first layer having a gallium-polar orientation with a top crystal plane consisting of a gallium face. A second layer including gallium and nitrogen is over a second region of the substrate, the second layer having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.

Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.

Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

Abstract: Gallium nitride (GaN) integrated circuit technology with multi-layer epitaxy and layer transfer is described. In an example, an integrated circuit structure includes a first channel structure including a plurality of alternating first channel layers and second channel layers, the first channel layers including gallium and nitrogen, and the second layers including gallium, aluminum and nitrogen. A second channel structure is bonded to the first channel structure. The second channel structure includes a plurality of alternating third channel layers and fourth channel layers, the third channel layers including gallium and nitrogen, and the fourth layers including gallium, aluminum and nitrogen.

Abstract: Gallium nitride (GaN) selective epitaxial windows for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width and a first height. A second trench is in the substrate, the second trench having a second width and a second height. The second width is greater than the first width, and the second height is greater than the first height. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate.

Abstract: Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

Abstract: Gallium nitride (GaN) layer transfer and regrowth for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate. An insulator layer is over the substrate. A device layer is directly on the insulator layer. The device layer has a thickness of less than approximately 500 nanometers.

Abstract: Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.

Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and on the first gate structure. In addition, at least a portion of the second gate structure is on a central portion of the isolation structure and between first and second end portions of the isolation structure.

Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

Abstract: Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.