Patents by Inventor Nikhil Jain

Nikhil Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230268389
    Abstract: Provided is a semiconductor device. The semiconductor device comprises a transistor comprising a plurality of source/drain epitaxies. The semiconductor device further comprises at least one backside power rail under the transistor. The semiconductor device further comprises a backside inter-layer dielectric (ILD) located between the plurality of source/drain epitaxies and the at least one power rail. The semiconductor device further comprises a first backside contact connecting a first source/drain epitaxy to the at least one backside power rail. The semiconductor device further comprises one or more contact placeholders formed under the other source/drain epitaxies.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Inventors: Nikhil Jain, Sagarika Mukesh, Devika Sarkar Grant, Prabudhya Roy Chowdhury, Ruilong Xie, Kisik Choi
  • Publication number: 20230222960
    Abstract: A pixel with a color-agnostic repair site includes a pixel controller, a first site for a first light emitter electrically connected to the pixel controller with a first wire, a second site for a second light emitter electrically connected to the pixel controller with a second wire different from the first wire, and a repair site for a repair light emitter. A repair wire can independently electrically connect the repair site to the pixel controller. A repair wire can electrically connect the repair site to the first wire or to the second wire with a jumper. The repair site can electrically connect to the first wire or to the second wire. A first repair wire can electrically connect the repair site to the first wire, a second repair wire can electrically connect the repair site to the second wire, and one of these wires can be cut.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 13, 2023
    Inventors: Nikhil Jain, Ronald S. Cok, Christopher Andrew Bower
  • Publication number: 20230108482
    Abstract: A method for parallel predictive modelling includes receiving a configuration file associated with a predictive concept at a production layer of a predictive modelling platform, the predictive modelling platform comprising the production layer and a consumption layer connected by a distributed messaging system. The method further includes identifying, by the production layer, a job request based on the configuration file, sending the job request to the consumption layer as one of a plurality of job requests to be passed to a predictive model implemented by a processing container, wherein the predictive model is specified by the configuration file, obtaining, from the processing container, a forecast as an output of the predictive model, sending, by the distributed messaging system, the forecast to the production layer and determining, by the production layer, one or more values of the predictive concept based on the forecast and an operator specified by the configuration file.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 6, 2023
    Inventors: Rockford Yost, Ankur Gahlot, Nikhil Jain
  • Publication number: 20230094707
    Abstract: Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Richard C. Johnson, Alex Richard Hubbard, Vinay Pai, Cody J. Murray, Fee Li Lie, Nikhil Jain
  • Patent number: 11569134
    Abstract: A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: January 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Nikhil Jain, Hsueh-Chung Chen, Mary Claire Silvestre, Hosadurga Shobha
  • Publication number: 20220415523
    Abstract: In an approach, a processor receives device identification information corresponding to at least one device local to a location of a transaction. A processor receives notification of an infected user. A processor determines that the infected user is associated with the transaction. A processor identifies a second user from the device identification information. A processor sends a notification to the second user.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Richard C. Johnson, Alex Richard Hubbard, Cody J. Murray, Vinay Pai, Nikhil Jain
  • Patent number: 11527667
    Abstract: Tunnel junctions for multijunction solar cells are provided. According to an aspect of the invention, a tunnel junction includes a first layer including p-type AlGaAs, a second layer including n-type GaAs, wherein the second layer is a quantum well, and a third layer including n-type AlGaAs or n-type lattice matched AlGaInP. The quantum well can be GaAs or AlxGaAs with x being more than about 40%, and lattice matched GaInAsNSb in the Eg range of from about 0.8 to about 1.4 eV.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 13, 2022
    Assignees: Alliance for Sustainable Energy, LLC, The Regents of the University of California, A California Corporation
    Inventors: Nikhil Jain, Myles Aaron Steiner, John Franz Geisz, Emmett Edward Perl, Ryan Matthew France
  • Publication number: 20220394436
    Abstract: Described are techniques for sharing data among a group of mobile devices that are registered to the same user. In some instances, the shared data is sensor data captured by a mobile device or media content being processed by the mobile device. The mobile devices in the group are configured to wirelessly communicate with each other and to share status information. Using the status information, the mobile devices can keep each other updated as to the operational status of each individual mobile device and, in some aspects, the status of a mobile device with respect to the user. The sensor data or media content can be forwarded to a different mobile device in response to a determination made based on the status information. For instance, forwarding can be based on a rule that specifies one or more conditions relating to the status of a mobile device and/or user status.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 8, 2022
    Inventors: Nikhil JAIN, Justin McGLOIN, Joel LINSKY, James Robert CHAPMAN
  • Publication number: 20210320036
    Abstract: A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 14, 2021
    Inventors: Nikhil JAIN, Hsueh-Chung CHEN, Mary Claire SILVESTRE, Hosadurga SHOBHA
  • Patent number: 11075313
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: July 27, 2021
    Assignee: UTICA LEASECO, LLC
    Inventors: Nikhil Jain, Andrew J. Ritenour, Ileana Rau, Claudio Canizares, Lori D. Washington, Gang He, Brendan M. Kayes
  • Patent number: 10873001
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 22, 2020
    Assignee: ALTA DEVICES, INC.
    Inventors: Nikhil Jain, Andrew J. Ritenour, Ileana Rau, Claudio Canizares, Lori D. Washington, Gang He, Brendan M. Kayes
  • Patent number: 10797197
    Abstract: A thin film, flexible optoelectronic device is described. In an aspect, a method for fabricating a single junction optoelectronic device includes forming a p-n structure on a substrate, the p-n structure including a semiconductor having a lattice constant that matches a lattice constant of substrate, the semiconductor including a dilute nitride, and the single-junction optoelectronic device including the p-n structure; and separating the single-junction optoelectronic device from the substrate. The dilute nitride includes one or more of GaInNAs, GaInNAsSb, alloys thereof, or derivatives thereof.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 6, 2020
    Assignee: ALTA DEVICES, INC.
    Inventors: Nikhil Jain, Brendan M. Kayes, Gang He
  • Publication number: 20200146516
    Abstract: A foam dispenser includes an air pump for pumping and outputting air, a liquid pump for pumping and outputting liquid soap, a mixing chamber for receiving the liquid soap and the air, and a controller for inversely controlling the outputs of the liquid pump and the air pump. A method of controlling the quality of foam produced by a foam dispenser including a liquid soap pump and an air pump includes simultaneously inversely varying the output of each of the pump for adjusting the quality of the foam produced.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 14, 2020
    Inventors: Dikran Babikian, Nikhil Jain
  • Patent number: 10624504
    Abstract: A foam dispenser includes an air pump for pumping and outputting air, a liquid pump for pumping and outputting liquid soap, a mixing chamber for receiving the liquid soap and the air, and a controller for inversely controlling the outputs of the liquid pump and the air pump. A method of controlling the quality of foam produced by a foam dispenser including a liquid soap pump and an air pump includes simultaneously inversely varying the output of each of the pump for adjusting the quality of the foam produced.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: April 21, 2020
    Assignee: BOBRICK WASHROOM EQUIPMENT, INC.
    Inventors: Dikran Babikian, Nikhil Jain
  • Publication number: 20200119222
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 16, 2020
    Inventors: Nikhil JAIN, Andrew J. RITENOUR, Ileana RAU, Claudio CANIZARES, Lori D. WASHINGTON, Gang HE, Brendan M. KAYES
  • Publication number: 20200119216
    Abstract: A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 16, 2020
    Inventors: Nikhil JAIN, Andrew J. RITENOUR, Ileana RAU, Claudio CANIZARES, Lori D. WASHINGTON, Gang HE, Brendan M. KAYES
  • Patent number: 10586884
    Abstract: A multi-junction optoelectronic device and method of fabrication are disclosed. In an aspect, the method includes forming a first p-n structure on a substrate, the first p-n structure including a semiconductor having a lattice constant that matches a lattice constant of the substrate; forming one or more additional p-n structures on the first p-n structure, each of the one or more additional p-n structures including a semiconductor having a lattice constant that matches the lattice constant of the substrate, the semiconductor of a last of the one or more additional p-n structures that is formed including a dilute nitride, and the multi-junction optoelectronic device including the first p-n structure and the one or more additional p-n structures; and separating the multi-junction optoelectronic device from the substrate. In some implementations, it is possible to have the dilute nitride followed by a group IV p-n structure.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 10, 2020
    Assignee: ALTA DEVICES, INC.
    Inventors: Nikhil Jain, Brendan M. Kayes, Gang He
  • Publication number: 20190386170
    Abstract: A multi junction optoelectronic device and method of fabrication are disclosed. In an aspect, the method includes forming a first p-n structure on a substrate, the first p-n structure including a semiconductor having a lattice constant that matches a lattice constant of the substrate; forming one or more additional p-n structures on the first p-n structure, each of the one or more additional p-n structures including a semiconductor having a lattice constant that matches the lattice constant of the substrate, the semiconductor of a last of the one or more additional p-n structures that is formed including a dilute nitride, and the multi junction optoelectronic device including the first p-n structure and the one or more additional p-n structures; and separating the multi junction optoelectronic device from the substrate. In some implementations, it is possible to have the dilute nitride followed by a group IV p-n structure.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 19, 2019
    Inventors: Nikhil JAIN, Brendan M. KAYES, Gang HE
  • Publication number: 20190386169
    Abstract: A thin film, flexible optoelectronic device is described. In an aspect, a method for fabricating a single junction optoelectronic device includes forming a p-n structure on a substrate, the p-n structure including a semiconductor having a lattice constant that matches a lattice constant of substrate, the semiconductor including a dilute nitride, and the single-junction optoelectronic device including the p-n structure; and separating the single-junction optoelectronic device from the substrate. The dilute nitride includes one or more of GaInNAs, GaInNAsSb, alloys thereof, or derivatives thereof.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 19, 2019
    Inventors: Nikhil Jain, Brendan M. Kayes, Gang He
  • Publication number: 20190272994
    Abstract: Aspects of the disclosure relate to processes for epitaxial growth of III-V compound of (Al)GaInP material at high rates, such as about 8 ?m/hr, 10 ?m/hr, 20 ?m/hr, 30 ?m/hr, 40 ?m/hr, and 8-120 ?m/hr deposition rates. The high growth-rate deposited (Al)InGaP materials or films may be utilized in solar, semiconductor, or other electronic device applications. The Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a chemical vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers containing gallium aluminum indium phosphide, gallium indium phosphide, derivatives thereof, alloys thereof, or combinations thereof.
    Type: Application
    Filed: May 14, 2019
    Publication date: September 5, 2019
    Inventors: Nikhil JAIN, Jason M. JEWELL, Chaowei WANG, Ji WU, Emmett Edward PERL, Claudio Andrés CAÑIZARES, Ling ZHANG, Brendan M. KAYES