Abstract: Systems and methods are provided for dynamic selection of anomaly detection options for particular metric data. Metric data corresponding to one or more configuration items of an information technology (IT) infrastructure is collected. A selected anomaly detection action option that applies to the metric data is identified. An action is performed using the metric data, based upon the selected anomaly detection action option. A dashboard graphical user interface (GUI) display results of the action.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

Abstract: A method for manufacturing integrated circuit (IC) devices includes forming first and second mask patterns with overlapping and non-overlapping features. Non-overlapping features may be removed before etching a target material layer. A third mask pattern may be formed from the overlapping features and used to etch a target material layer. The third mask pattern may be employed to make regular arrays of substantially rectangular structures. An IC device may include an IC die, an array of structures on a layer of the IC die, and multiple groups of parallel stripes of indentations or depressions in the layer. The structures may each include a transistor and a capacitor.

Abstract: Transistor structures with gate material self-aligned to underlying channel material. A channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. The channel mask material is then thinned to expose a sidewall of adjacent gate material. The exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. A third mask material may be formed in the expanded opening to protect an underlying portion of gate material during a gate etch that forms a trench bifurcating the underlying portion of gate material from an adjacent portion of gate material. The underlying portion of gate material extends laterally beyond the channel material by an amount that is substantially symmetrical about a centerline of the channel material and this amount has a height well controlled relative to the channel material.

Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut are described. For example, an integrated circuit structure includes a gate electrode over a vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. First and second dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure. The gate electrode has a zero edge placement error between the first dielectric cut plug structure and the second dielectric cut plug structure. An epitaxial source or drain structure is at an end of the vertical stack of horizontal nanowires and beneath the conductive trench contact.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: A patterning device for patterning product structures onto a substrate and an associated substrate patterned using such a patterning device. The patterning device includes target patterning elements for patterning at least one target from which a parameter of interest can be inferred. The patterning device includes product patterning elements for patterning the product structures. The target patterning elements and product patterning elements are configured such that the at least one target has at least one boundary which is neither parallel nor perpendicular with respect to the product structures on the substrate.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Abstract: Techniques for providing and implementing a single skill associated with custom functionality and system-provided functionality are described. The skill may be used to invoke functionality in response to a user input without requiring a user remember exact formulations to cause the functionality to be performed. The skill may be associated with more than one domain. For example, the skill may be associated with custom sample user inputs (corresponding to the custom functionality) that correspond to a custom domain while the skill may also be associated with system-provided sample user inputs (corresponding to the system-provided functionality) associated with a non-custom domain.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Abstract: Examples for detecting a compromised device are described. A set of threat detection rules can instruct an application on the client device how to detect whether the client device is compromised. The rules can be updated dynamically and without updating the application that is performing the compromise detection. The rules can be encoded in an interpreted scripting language and executed by a runtime environment that is embedded within the application.

Abstract: A lithographic apparatus includes an illumination system to produce a beam of radiation, a support to support a patterning device to impart a pattern on the beam, a projection system to project the patterned beam onto a substrate, and a metrology system that includes a radiation source to generate radiation, an optical element to direct the radiation toward a target, a detector to receive a first and second radiation scattered by the target and produce a first and second measurement respectively based on the received first and second radiation, and a controller. The controller determines a correction for the first measurement, an error between the correction for the first measurement and the first measurement, and a correction for the second measurement based on the correction for the first measurement, the second measurement, and the error. The lithographic apparatus uses the correction to adjust a position of a substrate.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: Methods and masks for manufacturing component of gas turbine engines are described. The methods include applying a mask to a protected surface of the component, the component having a designated surface to be treated by a shot peen operation. The mask includes a full masking portion configured to prevent a shot peen media from impacting the protected surface. A masking control region is arranged around the designated surface. The masking control region is configured to control an amount of force imparted to the component by shot peen media during the shot peen operation, wherein the masking control region extends from the full masking portion to the designated surface. The designated surface is shot peened with shot peen media to form a compressive stress region within the component proximate the designated surface and a tapering transition of compressive forces within the component proximate the masking control region.

Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

Abstract: Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires. The epitaxial growth occurs inside a mold confinement, and due the mold, the lateral wingspan of the wingspan of the epitaxial growth is limited. Also the mold causes the epitaxial source or drain structures to exhibit substantially vertical opposing sidewalls and a top surface having a generally mushroom shape over a top of a dielectric layer.