Patents by Inventor Nikhil Mehta
Nikhil Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200233870Abstract: The present approach relates generally to systems and methods for outputting metric data from resources with a database accessible by a client instance. The client instance is hosted by one or more data centers and accessible by one or more remote client networks. In accordance with the present approach, a request to track metric data related to a resource is received. Further, a configuration item (CI) is retrieved from a database accessible by the client instance based at least in part on data associated with the request. Further, a type of CI is identified. Even further, a resource type associated with the type of the CI is identified based at least in part on a resource abstraction layer accessible by the client instance. Further still, the resource type is linked to the resource table and metric data associated with the resource is outputted.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Inventors: Ritika Goyal, Szu-hsuan Lee, Vincent Seguin, Kanwaldeep Kaur Dang, Anand Nikhil Mehta
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Patent number: 10645191Abstract: Techniques are described for providing a content composing service that utilizes user feedback regarding network connectivity information or desired detail level to enhance content viewing and/or interacting. For example, content may be provided to a computing device in response to a request for content from the computing device. Further, input that indicates a desired detail level for the content may be received. The content may be modified based at least in part on the input and provided to the computing device. In embodiments, the modified content may be in accordance with the desired detail level indicated by the input. A graphical representation of the desired detail level for the content may be provided to the computing device.Type: GrantFiled: September 21, 2015Date of Patent: May 5, 2020Assignee: Amazon Technologies, Inc.Inventor: Nikhil Mehta
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Publication number: 20200092335Abstract: Examples for detecting a compromised device are described. A set of threat detection rules can instruct an application on the client device how to detect whether the client device is compromised. The rules can be updated dynamically and without updating the application that is performing the compromise detection. The rules can be encoded in an interpreted scripting language and executed by a runtime environment that is embedded within the application.Type: ApplicationFiled: September 18, 2018Publication date: March 19, 2020Inventors: Simon Brooks, Daniel E. Zeck, Xinpi Du, Ali Mohsin, Kishore Sajja, Nikhil Mehta
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Publication number: 20200092374Abstract: Examples herein describe systems and methods for on-device, application-specific compliance enforcement. An example method can include receiving, at a user device, an application having a compliance engine. The user device can also store a compliance rule that applies to the received application. The compliance rule can specify a condition and a remedial action for the application. The user device can execute the application. The application can determine, using the compliance engine within the application, whether the condition is present. The determination can be made regardless of whether the device has internet or cellular connectivity. Based on determining that the condition is present, the application can perform the remedial action.Type: ApplicationFiled: September 17, 2018Publication date: March 19, 2020Inventors: Nikhil Mehta, Sanjay Satagopan, Ali Mohsin, Simon Brooks, Ryan Turner, Lucas Chen
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Publication number: 20190303823Abstract: A centralized, computer implemented system is provided for request management within an organization, wherein the request management system is capable of performing the following functions: gathering user generated requests; sorting user generated requests; prioritising the requests; transferring the requests to the necessary person/department; updating the requester with the status of the request; linking related documents; matching requests relating to the same and/or similar items; and rejecting requests which are in violation of any pre-configured rules/limits.Type: ApplicationFiled: September 21, 2018Publication date: October 3, 2019Applicant: Zycus Infotech Pvt. Ltd.Inventors: Vijesh Bhakta, Nikhil Mehta
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Publication number: 20190268306Abstract: A portal application can receive a listing of available applications in response to a request sent to a management server. The listing can include a plurality of attributes for each available application, such as the requirements for using the features of each application or a dependency upon another application. Based on the plurality of attributes received, the portal application can determine that a first application requires installation of a second application in order for the first application to provide additional functionality. The portal application can display icons corresponding to the available applications and display one or more UI elements, indicating that the first application requires installation of the second application. The portal application can also push the second application to the device and assist in installing and initializing the second application on the device.Type: ApplicationFiled: February 26, 2018Publication date: August 29, 2019Inventors: Ujwal Naik, Soorya Rajasoorya, Nischit Shetty, Amit Yadav, Sanjay Satagopan, Sharath Chavva, Nidhi Aggarwal, Ryan Turner, Nikhil Mehta, Ali Mohsin
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Patent number: 6263452Abstract: A computer system in a fault-tolerant configuration employees multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.Type: GrantFiled: January 8, 1999Date of Patent: July 17, 2001Assignee: Compaq Computer CorporationInventors: Douglas E. Jewett, Tom Bereiter, Bryan Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, Krayn W. Fey, Jr., John Posdro, Kenneth C. Debacker, Nikhil A. Mehta
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Patent number: 6073251Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.Type: GrantFiled: June 9, 1997Date of Patent: June 6, 2000Assignee: Compaq Computer CorporationInventors: Douglas E. Jewett, Tom Bereiter, Bryan Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, deceased, Krayn W. Fey, Jr., John Posdro, Kenneth C. DeBacker, Nikhil A. Mehta
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Patent number: 5890003Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.Type: GrantFiled: September 7, 1993Date of Patent: March 30, 1999Assignee: Tandem Computers IncorporatedInventors: Richard W. Cutts, Jr., Kenneth C. Debacker, Robert W. Horst, Nikhil A. Mehta, Douglas E. Jewett, John David Allison, Richard A. Southworth
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Patent number: 5845060Abstract: A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.Type: GrantFiled: May 2, 1996Date of Patent: December 1, 1998Assignee: Tandem Computers, IncorporatedInventors: Richard Alan Vrba, James Stevens Klecka, Kyran Wilfred Fey, Jr., Larry Leonard Lamano, Nikhil A. Mehta
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Patent number: 5317752Abstract: A fault-tolerant computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. This powerfail/autorestart procedure may be implemented in a fault-tolerant multiprocessor configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.Type: GrantFiled: November 16, 1992Date of Patent: May 31, 1994Assignee: Tandem Computers IncorporatedInventors: Douglas E. Jewett, Phil Webster, Dave Aldridge, Peter C. Norwood, Nikhil A. Mehta
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Patent number: 5295258Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.Type: GrantFiled: January 5, 1990Date of Patent: March 15, 1994Assignee: Tandem Computers IncorporatedInventors: Douglas E. Jewett, Tom Bereiter, Brian Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, deceased, Kyran W. Fey, Jr., John Pozdro, Kenneth C. Debacker, Nikhil A. Mehta
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Patent number: 5193175Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.Type: GrantFiled: March 6, 1991Date of Patent: March 9, 1993Assignee: Tandem Computers IncorporatedInventors: Richard W. Cutts, Jr., Peter C. Norwood, Kenneth C. DeBacker, Nikhil A. Mehta, Douglas E. Jewett, John D. Allison, Robert W. Horst
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Patent number: 4965717Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. Memory references. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references by the multiple CPUs are voted by each of the memory modules. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.Type: GrantFiled: December 13, 1988Date of Patent: October 23, 1990Assignee: Tandem Computers IncorporatedInventors: Richard W. Cutts, Jr., Nikhil A. Mehta, Douglas E. Jewett