Abstract: A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.

Abstract: An electronic device comprises a central processing unit, a graphics processing unit, and a power control unit comprising logic to develop a predictive model of power states for a central processing unit in the electronic device, and use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit. Other embodiments may be described.

Abstract: Methods, systems and computer system products to allow audio decryption and decoding to be performed on a graphics engine instead of on a host processor. This may be accomplished without having to modify media application software. A down codec function driver exposes a down codec to a media application, which may then send encrypted and encoded audio data to the down codec function driver. The down codec function driver may then redirect the audio data to a graphics driver. The graphics driver may then pass the audio data to a graphics engine. The graphics engine may then decrypt and decode the audio data. The decrypted and decoded audio data may be returned to the graphics driver, which may then send the decrypted and decoded audio data to the function driver. The function driver may then pass the decrypted and decoded audio data to the down codec for rendering.

Abstract: Techniques are disclosed that involve the processing of audio streams. For instance, a host processing platform may receive a content stream that includes an encoded audio stream. In turn, a graphics engine produces from it a decoded audio stream. This producing may involve the graphics engine performing various operations, such as an entropy decoding operation, an inverse quantization operation, and an inverse discrete cosine transform operation. In embodiments, the content stream may further include an encoded video stream. Thus the graphics engine may produce from it a decoded video stream. This audio and video decoding may be performed in parallel.

Abstract: A method includes executing a workload on a graphics (GFX) core in a first mode the GFX core comprising a plurality of Subslices wherein each of the plurality of Subslices dissipates power. The method further includes calculating a number of clock cycles, Tfirst mode, required for the GFX core to perform the workload in the first mode during a first decision window comprising a plurality of clock cycles and calculating a number of clock cycles, Tsecond mode, required for the GFX core to perform the workload in a second mode during the first decision window wherein the second mode comprises executing the workload with fewer of the plurality of Subslices receiving power than when executing the workload in the first mode. It is then determined, based in part upon Tfirst mode and Tsecond mode, if an energy savings is possible by transitioning the GFX core to the second mode.

Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.

Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.

Abstract: Embodiments of a method and apparatus are described for low power operation of a multi-core processing system. An apparatus may comprise, for example, an affinitization management module operative to detect a media application operative to execute on one or more of a plurality of processor cores of a multi-core processor, dynamically select a subset of processor cores of the multi-core processor, and affinitize the media application to execute on the subset of processor cores. Other embodiments are described and claimed.

Abstract: An electronic device comprises a central processing unit, a graphics processing un and a power control unit comprising logic to develop a predictive model of power states for a central processing unit in the electronic device, and use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit. Other embodiments may be described.

Abstract: Embodiments of methods, apparatuses, and systems that enable power conservation in data buffering components are disclosed. Other embodiments may also be disclosed.

Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

Abstract: Embodiments of methods, apparatuses, and systems that enable power conservation in data buffering components are disclosed. Other embodiments may also be disclosed.

Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.

Abstract: In some embodiments, an electronic apparatus comprises a processor, at least one non-volatile memory module, and logic to activate a first DIMM while placing at least a second DIMM in a sleep mode, assign operating system memory to grow from a first location in a first DIMM device, assign application memory to grow from a second location in the first DIMM device, mark at least one DIMM boundary in the first DIMM device, generate a page fault when at least one of the operating system memory or the application memory crosses the DIMM boundary; and in response to the page fault, activate at least a second DIMM in the plurality of DIMMs in the electronic device.

Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

Abstract: A method and apparatus for gating a clock signal to one or more embedded blocks of a random access memory (RAM), is described. In one embodiment, a clock gating block is coupled to a RAM EBB, the clock-gating block to provide a RAM clock when receiving read and write enable signals and to provide a gated clock signal when the RAM EBB is idle. In another embodiment, a clock gating block is coupled to a RAM bank, having a plurality of RAM EBBs, the clock-gating block to provide a RAM clock to the RAM bank when receiving read and write enable signals and to provide a gated clock signal to the RAM bank when the RAM bank is idle.

Abstract: A method and apparatus for gating a clock signal to one or more embedded blocks of a random access memory (RAM), is described. In one embodiment, a clock gating block is coupled to a RAM EBB, the clock-gating block to provide a RAM clock when receiving read and write enable signals and to provide a gated clock signal when the RAM EBB is idle. In another embodiment, a clock gating block is coupled to a RAM bank, having a plurality of RAM EBBs, the clock-gating block to provide a RAM clock to the RAM bank when receiving read and write enable signals and to provide a gated clock signal to the RAM bank when the RAM bank is idle.

Abstract: A method and system for performing integrated adjustable short-haul/long-haul time domain reflectometry (TDR). A TDR pulse count is set to a predetermined number. Next, a TDR pulse is transmitted through a cable. The width of the TDR pulse is a function of the multiplication of the TDR pulse count with the period of a TDR clock. It is then determined whether the TDR pulse has been reflected back. If the TDR pulse has not been reflected, the TDR pulse count is successively increased to successively increase the width of the transmitted TDR pulse until a reflection is detected—indicating an open in the cable. Furthermore, it eliminates false detections of cable opens. Moreover, the system can be combined into a line interface unit (LIU) integrated circuit such that TDR functionality can be performed automatically without the use of a technician.