Patents by Inventor Nikos Kaburlasos

Nikos Kaburlasos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180293779
    Abstract: An embodiment of a parallel processor apparatus may include a sample pattern selector to select a sample pattern for a pixel, and a sample pattern subset selector communicatively coupled to the sample pattern selector to select a first subset of the sample pattern for the pixel corresponding to a left eye display frame and to select a second subset of the sample pattern for the pixel corresponding to a right eye display frame, wherein the second subset is different from the first subset. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws
  • Publication number: 20180284872
    Abstract: An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Kamal Sinha, James M. Holland, Pattabhiraman K., Sayan Lahiri, Radhakrishnan Venkataraman, Carson Brownlee, Vivek Tiwari, Kai Xiao, Jefferson Amstutz, Deepak S. Vembar, Ankur N. Shah, ElMoustapha Ould-Ahmed-Vall
  • Publication number: 20180286006
    Abstract: An apparatus for tile reuse in imaging is described herein. The apparatus a memory, a line based processing system, a block based processing system, and a tile reuse indicator. The memory is to store imaging data. The line-based processing system is to process lines of imaging data and store the processed data in memory and the block-based processing system is to process blocks of the line based processed imaging data and storing the processed data in memory. The tile reuse indicator is to determine an unchanged tile of the imaging data, and in response to an unchanged tile prevent further processing of the unchanged tile.
    Type: Application
    Filed: April 3, 2017
    Publication date: October 4, 2018
    Applicant: INTEL CORPORATION
    Inventors: Nikos Kaburlasos, Kinchit Desai, Sanjeev S. Jahagirdar
  • Publication number: 20180285158
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Abhishek R. Appu, Altug Koker, Balaji Vembu, Joydeep Ray, Kamal Sinha, Prasoonkumar Surti, Kiran C. Veernapu, Subramaniam Maiyuran, Sanjeev S. Jahagirdar, Eric J. Asperheim, Guei-Yuan Lueh, David Puffer, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Josh B. Mastronarde, Linda L. Hurd, Travis T. Schluessler, Tomasz Janczak, Abhishek Venkatesh, Kai Xiao, Slawomir Grajewski
  • Publication number: 20180285230
    Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Nikos Kaburlasos, Balaji Vembu, Josh B. Mastronarde, Altug Koker, Eric C. Samson, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Vasanth Ranganathan, Sanjeev S. Jahagirdar
  • Publication number: 20180284871
    Abstract: Methods and apparatus relating to techniques for shutting down one or more GPU (Graphics Processing Unit) components in response to unchanged scene detection are described. In one embodiment, one or more components of a processor enter a low power consumption state in response to a determination that a scene to be displayed is static. The static scene is displayed on a display device (e.g., based on information to be retrieved from memory) for as long as no change to the static scene is detected. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall, Deepak S. Vembar, Abhishek R. Appu, Ankur N. Shah
  • Publication number: 20180286024
    Abstract: Systems, apparatuses, and methods may provide for technology to process multi-resolution images by identifying pixels at a boundary between pixels of different resolutions, and selectively smoothing the identified pixels.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski
  • Publication number: 20180284868
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Publication number: 20180286105
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Patent number: 10080095
    Abstract: A camera input can be used by the computer to support audio spatialization or to improve audio spatialization of an application that already supports it. A computer system may to support audio spatialization, for example, by modifying the relative latency or relative amplitude of the rendered audio packets. If a sound is intended, for example, to be located on the left side of the user, then the audio channel that is rendered on the headset speaker located on the user's left ear may have a somewhat decreased latency and increased amplitude compared to the other audio channel.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Devon Worrell
  • Patent number: 10025367
    Abstract: In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: July 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Nikos Kaburlasos, Eric Samson
  • Patent number: 10014046
    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Jim Kardach, Nikos Kaburlasos
  • Patent number: 9942593
    Abstract: Techniques are disclosed that involve the processing of audio streams. For instance, a host processing platform may receive a content stream that includes an encoded audio stream. In turn, a graphics engine produces from it a decoded audio stream. This producing may involve the graphics engine performing various operations, such as an entropy decoding operation, an inverse quantization operation, and an inverse discrete cosine transform operation. In embodiments, the content stream may further include an encoded video stream. Thus the graphics engine may produce from it a decoded video stream. This audio and video decoding may be performed in parallel.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Hong Jiang, Michael D. Stoner, Narayan Biswal
  • Patent number: 9805438
    Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson, Altug Koker
  • Patent number: 9596555
    Abstract: A camera input can be used by the computer to support audio spatialization or to improve audio spatialization of an application that already supports it. A computer system may to support audio spatialization, for example, by modifying the relative latency or relative amplitude of the rendered audio packets. If a sound is intended, for example, to be located on the left side of the user, then the audio channel that is rendered on the headset speaker located on the user's left ear may have a somewhat decreased latency and increased amplitude compared to the other audio channel.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Devon Worrell
  • Publication number: 20160366532
    Abstract: A camera input can be used by the computer to support audio spatialization or to improve audio spatialization of an application that already supports it. A computer system may to support audio spatialization, for example, by modifying the relative latency or relative amplitude of the rendered audio packets. If a sound is intended, for example, to be located on the left side of the user, then the audio channel that is rendered on the headset speaker located on the user's left ear may have a somewhat decreased latency and increased amplitude compared to the other audio channel.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Devon Worrell
  • Patent number: 9519946
    Abstract: In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson, Robert B. Taylor
  • Publication number: 20160225120
    Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.
    Type: Application
    Filed: January 12, 2016
    Publication date: August 4, 2016
    Inventors: Nikos Kaburlasos, Eric C. Samson, Altug Koker
  • Publication number: 20160093013
    Abstract: Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 31, 2016
    Inventors: Nikos Kaburlasos, Eric C. Samson
  • Patent number: 9275601
    Abstract: Techniques to determine when to decrease a frame display rate based in part on the amount or degree of change between sequential frames. The amount or degree of change can be measured based on all or part of similarly located portions of sequential frames. In some cases, power use can be reduced without compromising visual quality by reducing frame display rate when an amount or degree of change between frames is small.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric Samson