Patents by Inventor Nikos Kaburlasos

Nikos Kaburlasos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160054782
    Abstract: In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.
    Type: Application
    Filed: August 19, 2014
    Publication date: February 25, 2016
    Inventors: NIKOS KABURLASOS, Eric Samson
  • Patent number: 9269120
    Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson, Altug Koker
  • Patent number: 9253524
    Abstract: In general, in one aspect, a graphics driver receives information related to where eyes of a user watching a video are focused, determine if the user is focusing their attention on a particular location of the video, and generates post processing instructions for pixel macro blocks of decoded video frames. The instructions are based on whether it is determined that the user is focused. The graphics driver is further to determine a focus area associated with the particular location the user is focusing their attention on, determine a peripheral area around the focus area, generate a first set of post processing instructions for pixel macro blocks within the focus area, generate a second set of post processing instructions for pixel macro blocks within the peripheral area, and generate a third set of post processing instructions for pixel macro blocks not within either area.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Scott Janus, Michael A. Smith
  • Publication number: 20150357025
    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
    Type: Application
    Filed: May 13, 2015
    Publication date: December 10, 2015
    Applicant: Intel Corporation
    Inventors: Jim Kardach, Nikos Kaburlasos
  • Publication number: 20150332428
    Abstract: In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.
    Type: Application
    Filed: July 28, 2015
    Publication date: November 19, 2015
    Inventors: Nikos Kaburlasos, Eric C. Samson, Robert B. Taylor
  • Publication number: 20150279055
    Abstract: A system and method are described herein. The method includes fetching a portion of a first level of detail (LOD) and a delta. A portion of a second LOD is predicted using the portion of the first LOD. The second LOD is reconstructed using the predicted portion of the second LOD and the delta.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: NIKOS KABURLASOS, YOAV HAREL, BENJAMIN R. PLETCHER
  • Patent number: 9123088
    Abstract: In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson, Robert B. Taylor
  • Patent number: 9058894
    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 16, 2015
    Assignee: INTEL CORPORATION
    Inventors: Jim Kardach, Nikos Kaburlasos
  • Publication number: 20150035853
    Abstract: In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Inventors: Nikos Kaburlasos, Eric C. Samson, Robert B. Taylor
  • Patent number: 8924756
    Abstract: A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson, David Puffer, Lakshminarayan Jagannathan
  • Publication number: 20140347363
    Abstract: In accordance with some embodiments, processing power is applied based on the user's detected level of interest. In one embodiment, the user's detected level of interest in particular regions within a frame may be determined using an eye gaze detector or eye tracking apparatus. Those frame regions or areas that the user spends more of his or her attention on may be processed faster, at higher resolution or otherwise to enhance their depiction.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Inventor: Nikos Kaburlasos
  • Patent number: 8843702
    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Jlm Kardach, Nikos Kaburlasos
  • Patent number: 8806243
    Abstract: A method includes executing a workload on a graphics (GFX) core in a first mode the GFX core comprising a plurality of Subslices wherein each of the plurality of Subslices dissipates power. The method further includes calculating a number of clock cycles, Tfirst mode, required for the GFX core to perform the workload in the first mode during a first decision window comprising a plurality of clock cycles and calculating a number of clock cycles, Tsecond mode, required for the GFX core to perform the workload in a second mode during the first decision window wherein the second mode comprises executing the workload with fewer of the plurality of Subslices receiving power than when executing the workload in the first mode. It is then determined, based in part upon Tfirst mode and Tsecond mode, if an energy savings is possible by transitioning the GFX core to the second mode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson
  • Publication number: 20140160136
    Abstract: Techniques to determine when to decrease a frame display rate based in part on the amount or degree of change between sequential frames. The amount or degree of change can be measured based on all or part of similarly located portions of sequential frames. In some cases, power use can be reduced without compromising visual quality by reducing frame display rate when an amount or degree of change between frames is small.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Inventors: Nikos Kaburlasos, Eric Samson
  • Publication number: 20140125679
    Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Inventors: Nikos Kaburlasos, Eric C. Samson, Altug Koker
  • Publication number: 20140115248
    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 24, 2014
    Inventors: Jim Kardach, Nikos Kaburlasos
  • Publication number: 20140023351
    Abstract: In general, in one aspect, a graphics driver receives information related to where eyes of a user watching a video are focused, determine if the user is focusing their attention on a particular location of the video, and generates post processing instructions for pixel macro blocks of decoded video frames. The instructions are based on whether it is determined that the user is focused. The graphics driver is further to determine a focus area associated with the particular location the user is focusing their attention on, determine a peripheral area around the focus area, generate a first set of post processing instructions for pixel macro blocks within the focus area, generate a second set of post processing instructions for pixel macro blocks within the peripheral area, and generate a third set of post processing instructions for pixel macro blocks not within either area.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Scott Janus, Michael A. Smith
  • Patent number: 8607083
    Abstract: Embodiments of a method and apparatus are described for low power operation of a multi-core processing system. An apparatus may comprise, for example, an affinitization management module operative to detect a media application operative to execute on one or more of a plurality of processor cores of a multi-core processor, dynamically select a subset of processor cores of the multi-core processor, and affinitize the media application to execute on the subset of processor cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Guy M Therien
  • Publication number: 20130286026
    Abstract: Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.
    Type: Application
    Filed: November 21, 2011
    Publication date: October 31, 2013
    Inventors: Nikos Kaburlasos, Eric C. Samson
  • Publication number: 20130064376
    Abstract: A camera input can be used by the computer to support audio spatialization or to improve audio spatialization of an application that already supports it. A computer system may to support audio spatialization, for example, by modifying the relative latency or relative amplitude of the rendered audio packets. If a sound is intended, for example, to be located on the left side of the user, then the audio channel that is rendered on the headset speaker located on the user's left ear may have a somewhat decreased latency and increased amplitude compared to the other audio channel.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 14, 2013
    Inventors: Nikos Kaburlasos, Scott W. Cheng, Devon Worrell