Patents by Inventor Nilanjan Mukherjee

Nilanjan Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327139
    Abstract: Methods for CAD operations and corresponding systems (2100) and computer-readable mediums (2126) are disclosed herein. A method (2000) includes receiving model data (2002) of a surface (210) of a part (200) to be manufactured. The method includes performing a loop-paving process (2004) for a first portion of the surface (210) to produce a first set of elements (302, 304, 306). The method includes performing a Cartesian meshing process (2010) for a second portion of the surface (210) to produce a second set of elements (704). The method includes performing a subdivision meshing process (2016) for a third portion of the surface (210) to produce a third set of elements (1002). The method includes combining (2020) the first set of elements (302, 304, 306), the second set of elements (704), and the third set of elements (1002) to produce a final mesh (1202) for the surface (210) of the part (200) to be manufactured.
    Type: Application
    Filed: September 21, 2018
    Publication date: October 21, 2021
    Inventor: Nilanjan Mukherjee
  • Patent number: 11126766
    Abstract: A system and method is provided for element quality improvement in three-dimensional (3D) quadrilateral-dominant surface meshes. The system may include a processor configured to collapse a first plurality of edges of a plurality of quadrilateral elements that form a surface mesh of a 3D model, which edges have lengths that are shorter than a predetermined fraction of a minimum element edge length (MEL). Further, the processor may also move nodes connected to at least some of a second plurality of edges of the plurality of quadrilateral elements so as to have lengths that are at least the MEL. Also, the processor may adjust included angles and the warp of elements to be within predetermined limits. Further, the processor may collapse in the mesh all remaining edges of the plurality of quadrilateral elements that are shorter than the MEL to produce a modified surface mesh in which all quadrilaterals in the modified mesh have edge lengths that are at least the MEL.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 21, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Jonathan Makem, Nilanjan Mukherjee
  • Publication number: 20210156918
    Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.
    Type: Application
    Filed: November 17, 2020
    Publication date: May 27, 2021
    Inventors: Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
  • Publication number: 20210150112
    Abstract: A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.
    Type: Application
    Filed: October 28, 2020
    Publication date: May 20, 2021
    Inventors: Yu Huang, Janusz Rajski, Mark A. Kassab, Nilanjan Mukherjee, Jeffrey Mayer
  • Publication number: 20210103685
    Abstract: A system and method is provided for element quality improvement in three-dimensional (3D) quadrilateral-dominant surface meshes. The system may include a processor configured to collapse a first plurality of edges of a plurality of quadrilateral elements that form a surface mesh of a 3D model, which edges have lengths that are shorter than a predetermined fraction of a minimum element edge length (MEL). Further, the processor may also move nodes connected to at least some of a second plurality of edges of the plurality of quadrilateral elements so as to have lengths that are at least the MEL. Also, the processor may adjust included angles and the warp of elements to be within predetermined limits. Further, the processor may collapse in the mesh all remaining edges of the plurality of quadrilateral elements that are shorter than the MEL to produce a modified surface mesh in which all quadrilaterals in the modified mesh have edge lengths that are at least the MEL.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 8, 2021
    Inventors: Jonathan Makem, Nilanjan Mukherjee
  • Patent number: 10963612
    Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 30, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Nilanjan Mukherjee, Jedrzej Solecki, Janusz Rajski
  • Patent number: 10955460
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
  • Patent number: 10956625
    Abstract: A system and method is provided that facilitates generating meshes for object models of structures for use with finite element analysis simulations carried out on the structure. The system may include at least one processor configured to classify a type of an input face of a three dimensional (3D) object model of a structure based at least in part on a number of loops included by the input face. The processor may also select based on the classified type of the input face a multi-block decomposition algorithm from among a plurality of multi-block decomposition algorithms that the processor is configured to use. Further the processor may use the selected multi-block decomposition algorithm to determine locations of a plurality of blocks across the input face. In addition the processor may mesh each block to produce mesh data defining a mesh that divides the input face into a plurality of quadrilateral elements.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: March 23, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Jonathan Makem, Nilanjan Mukherjee
  • Publication number: 20200327268
    Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.
    Type: Application
    Filed: April 10, 2020
    Publication date: October 15, 2020
    Inventors: Nilanjan Mukherjee, Jedrzej Solecki, Janusz Rajski
  • Patent number: 10509072
    Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10444282
    Abstract: Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: October 15, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10361873
    Abstract: Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: July 23, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Nilanjan Mukherjee, Elham K. Moghaddam, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10277422
    Abstract: A tool for assigning virtual port channels to one or more logical switch routers in a distributed system. The tool receives, by one or more computer processors, a request to assign a virtual port channel to a second logical switch router. The tool sends, by one or more computer processors, a request to negotiate a link-down on the channel on a first logical switch router to a universal fiber port on the first logical switch router for processing. The tool sends, by one or more computer processors, a request to create the channel on the second logical switch router to a second interface manager on the second logical switch router for processing. The tool sends, by one or more computer processors, a request to negotiate a link up on the channel on the second logical switch router to the universal fiber port on the first logical switch router for processing.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ashok N. Chippa, Ioana M. Costea, Vipin K. Garg, Sze W. Lao, Dar-Ren Leu, Nilanjan Mukherjee, Vijoy A. Pandey, Daljeet Singh, Ethan M. Spiegel, Robert E. Zagst, Jr.
  • Patent number: 10234506
    Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 19, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
  • Patent number: 10148569
    Abstract: In one embodiment, a system includes at least one processor and logic integrated with and/or executable by the at least one processor, the logic being configured to receive, by the at least one processor, a request to assign a media access control (MAC) address to a device on a port, determine, by the at least one processor, the MAC address to assign to the device based at least partially on the port, and send, by the at least one processor, a response to the request with the MAC address. According to a further embodiment, the logic may be configured to create a MAC address allocation table that includes a plurality of hash values, each hash value being associated with one port and a plurality of MAC addresses, wherein the assigned MAC address is one of the MAC addresses associated with the port in the MAC address allocation table.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Sushma Anantharam, Keshav G. Kamble, Dar-Ren Leu, Nilanjan Mukherjee, Vijoy A. Pandey
  • Publication number: 20180252768
    Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.
    Type: Application
    Filed: January 30, 2018
    Publication date: September 6, 2018
    Inventors: Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
  • Publication number: 20180143249
    Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Applicant: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee
  • Patent number: 9874606
    Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: January 23, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee
  • Publication number: 20180017622
    Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    Type: Application
    Filed: May 30, 2017
    Publication date: January 18, 2018
    Applicant: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
  • Patent number: 9787608
    Abstract: A method and system for configuring communications over a physical communication link connected between a physical port of a network switch and a physical port of a physical network interface on an end station. The communication link between the physical port of the network switch and the physical port of the physical network interface is logically partitioned into a number of channels of communication. For each channel, a channel profile is generated that defines properties of that channel. The physical network interface is instructed to self-configure such that the physical network interface is able to communicate with the network switch over each channel in accordance with the channel profile defined for that channel.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jayakrishna Kidambi, Nilanjan Mukherjee, Vijoy Pandey