Abstract: A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.

Abstract: Methods for CAD operations and corresponding systems (2100) and computer-readable mediums (2126) are disclosed herein. A method (2000) includes receiving model data (2002) of a surface (210) of a part (200) to be manufactured. The method includes performing a loop-paving process (2004) for a first portion of the surface (210) to produce a first set of elements (302, 304, 306). The method includes performing a Cartesian meshing process (2010) for a second portion of the surface (210) to produce a second set of elements (704). The method includes performing a subdivision meshing process (2016) for a third portion of the surface (210) to produce a third set of elements (1002). The method includes combining (2020) the first set of elements (302, 304, 306), the second set of elements (704), and the third set of elements (1002) to produce a final mesh (1202) for the surface (210) of the part (200) to be manufactured.

Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

Abstract: A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

Abstract: Methods for CAD operations and corresponding systems (2800) and computer-readable mediums (2826) are disclosed herein. A method includes receiving (502) a model (600) of a part to be manufactured, wherein the model includes a plurality of original faces (102, 104, 106, 112, 114). The method includes classifying (510) each face in model according to a relative face curvature according to classifications that include at least a high-curvature classification (702). The method includes classifying (514) any sliver faces (102, 104, 106, 112, 114) and narrow blend faces (402, 404, 406, 408) of the plurality of faces. The method includes merging (516) contiguous faces (702) in each classification. The method includes detecting (518) special faces (1002, 1012) of the plurality of faces. The method includes restoring (520) original faces in the high-curvature classification except for the special faces (1002, 1012).

Abstract: A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.

Abstract: A computer-implemented method of modifying a finite element mesh. The method includes providing an original-input-orphan-mesh, selecting and extracting at least a part of the original-input-orphan-mesh as an orphan-element-patch-object, generating faces on the orphan-element-patch-object as a faces-on-mesh-object geometry, generating a new mesh patch element based on the faces-on-mesh-object-geometry and at least one changed meshing-parameter. The changed meshing-parameter is assigned to generate a new mesh patch element that is different to the corresponding original-input-orphan-mesh. The method further includes generating an amended orphan mesh by replacing the orphan-element-patch-object of the original-input-orphan-mesh by the new mesh patch element.

Abstract: A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Abstract: A system for testing a circuit comprises scan chains, a controller configured to generate a bit- inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

Abstract: Methods for CAD operations and corresponding systems (2800) and computer-readable mediums (2826) are disclosed herein. A method includes receiving (502) a model (600) of a part to be manufactured, wherein the model includes a plurality of original faces (102, 104, 106, 112, 114). The method includes classifying (510) each face in model according to a relative face curvature according to classifications that include at least a high-curvature classification (702). The method includes classifying (514) any sliver faces (102, 104, 106, 112, 114) and narrow blend faces (402, 404, 406, 408) of the plurality of faces. The method includes merging (516) contiguous faces (702) in each classification. The method includes detecting (518) special faces (1002, 1012) of the plurality of faces. The method includes restoring (520) original faces in the high-curvature classification except for the special faces (1002, 1012).

Abstract: Methods for CAD operations and corresponding systems (2100) and computer-readable mediums (2126) are disclosed herein. A method (2000) includes receiving model data (2002) of a surface (210) of a part (200) to be manufactured. The method includes performing a loop-paving process (2004) for a first portion of the surface (210) to produce a first set of elements (302, 304, 306). The method includes performing a Cartesian meshing process (2010) for a second portion of the surface (210) to produce a second set of elements (704). The method includes performing a subdivision meshing process (2016) for a third portion of the surface (210) to produce a third set of elements (1002). The method includes combining (2020) the first set of elements (302, 304, 306), the second set of elements (704), and the third set of elements (1002) to produce a final mesh (1202) for the surface (210) of the part (200) to be manufactured.

Abstract: A system and method is provided for element quality improvement in three-dimensional (3D) quadrilateral-dominant surface meshes. The system may include a processor configured to collapse a first plurality of edges of a plurality of quadrilateral elements that form a surface mesh of a 3D model, which edges have lengths that are shorter than a predetermined fraction of a minimum element edge length (MEL). Further, the processor may also move nodes connected to at least some of a second plurality of edges of the plurality of quadrilateral elements so as to have lengths that are at least the MEL. Also, the processor may adjust included angles and the warp of elements to be within predetermined limits. Further, the processor may collapse in the mesh all remaining edges of the plurality of quadrilateral elements that are shorter than the MEL to produce a modified surface mesh in which all quadrilaterals in the modified mesh have edge lengths that are at least the MEL.

Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

Abstract: A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Abstract: A system and method is provided for element quality improvement in three-dimensional (3D) quadrilateral-dominant surface meshes. The system may include a processor configured to collapse a first plurality of edges of a plurality of quadrilateral elements that form a surface mesh of a 3D model, which edges have lengths that are shorter than a predetermined fraction of a minimum element edge length (MEL). Further, the processor may also move nodes connected to at least some of a second plurality of edges of the plurality of quadrilateral elements so as to have lengths that are at least the MEL. Also, the processor may adjust included angles and the warp of elements to be within predetermined limits. Further, the processor may collapse in the mesh all remaining edges of the plurality of quadrilateral elements that are shorter than the MEL to produce a modified surface mesh in which all quadrilaterals in the modified mesh have edge lengths that are at least the MEL.

Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.

Abstract: A system and method is provided that facilitates generating meshes for object models of structures for use with finite element analysis simulations carried out on the structure. The system may include at least one processor configured to classify a type of an input face of a three dimensional (3D) object model of a structure based at least in part on a number of loops included by the input face. The processor may also select based on the classified type of the input face a multi-block decomposition algorithm from among a plurality of multi-block decomposition algorithms that the processor is configured to use. Further the processor may use the selected multi-block decomposition algorithm to determine locations of a plurality of blocks across the input face. In addition the processor may mesh each block to produce mesh data defining a mesh that divides the input face into a plurality of quadrilateral elements.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.

Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.

Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.