Abstract: Methods and devices for using high-speed serial links for scan testing are disclosed. The methods can work with any scheme of scan data compression or with uncompressed scan testing. The protocol and hardware to support high speed data transfer reside on both the tester and the device under test. Control data may be transferred along with scan data or be partially generated on chip. Clock signals for testing may be generated on chip as well. In various implementations, the SerDes (Serializer/Deserializer) may be shared with other applications. The Aurora Protocol may be used to transport industry standard protocols. To compensate for effects of asynchronous operation of a conventional high-speed serial link, buffers may be used. The high-speed serial interface may use a data conversion block to drive test cores.

Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

Abstract: A switching network has a plurality of switches including at least a switch and a managing master switch. At the managing master switch, a first capability vector (CV) is received from the switch. The managing master switch determines whether the first CV is compatible with at least a second CV in a network membership data structure that records CVs of multiple switches in the switching network. In response to detecting an incompatibility, the managing master switch initiates an image update to an image of the switch. In response to a failure of the image update at the switch, the switch boots utilizing a mini-DC module that reestablishes communication between the switch with the managing master switch and retries the image update.

Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.

Abstract: In one embodiment, a system includes a network having a plurality of switches and one or more devices connected to one or more of the plurality of switches, a software defined network (SDN) controller connected to one or more of the plurality of switches in the network, the SDN controller having logic integrated with and/or executable by a processor, the logic being adapted to determine SDN routes through the network between the one or more devices and each of the plurality of switches and send one or more SDN routes to each switch in the network capable of communicating with the SDN controller. In other embodiments, methods and computer program products are also described for providing SDN routes through a network.

Abstract: In one embodiment, a system includes at least one processor which includes logic configured for receiving a request to assign a media access control (MAC) address to a device on a port, logic configured for determining the MAC address to assign to the device based at least partially on the port, and logic configured for sending a response to the request with the MAC address. In another embodiment, a computer program product for assigning a MAC address includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code including computer readable program code configured for determining, without using a look-up table, a MAC address to assign to a device and computer readable program code configured for sending the MAC address to the device. Other systems, methods, and computer program products are presented according to more embodiments.

Abstract: A communication protocol in a layer two (L2) network switch comprises, in response to a service request by a source node, registering the source node for packet communication service. The protocol further comprises forwarding one or more packets from the registered source node to one or more destination nodes. The protocol further comprises receiving packets from one or more destination nodes and forwarding each received packet to a corresponding registered node.

Abstract: A communication protocol in a layer two (L2) network switch comprises, in response to a service request by a source node, registering the source node for packet communication service. The protocol further comprises forwarding one or more packets from the registered source node to one or more destination nodes. The protocol further comprises receiving packets from one or more destination nodes and forwarding each received packet to a corresponding registered node.

Abstract: According to one embodiment, a system includes a scalable virtual appliance cloud (SVAC) comprising: at least one distributed line card (DLC); at least one switch fabric coupler (SFC) in communication with the at least one DLC; and at least one controller in communication with the at least one DLC, wherein one or more of the at least one DLC is an appliance DLC, wherein one or more of the at least one SFC is a central SFC, and wherein the SVAC appears to a device external of the SVAC as a single appliance device applying various services to a traffic flow.

Abstract: According to one embodiment, a method for providing scalable virtual appliance cloud (SVAC) services includes receiving incoming data traffic having multiple packets directed toward a SVAC using at least one switching distributed line card (DLC), determining that a packet satisfies a condition of an access control list (ACL), designating a destination port to send the packet based on the condition of the ACL being satisfied, fragmenting the packet into cells, wherein the designated destination port is stored in a cell header of the cells, sending the cells to the destination port via at least one switch fabric controller (SFC), receiving the cells at a fabric interface of an appliance DLC, reassembling the cells into a second packet, performing one or more services on the second packet using the appliance DLC, and sending the second packet to its intended port.

Abstract: A distributed fabric system has distributed line card (DLC) chassis and scaled-out fabric coupler (SFC) chassis. Each DLC chassis includes a network processor and fabric ports. Each network processor of each DLC chassis includes a fabric interface in communication with the DLC fabric ports of that DLC chassis. Each SFC chassis includes a fabric element and fabric ports. A communication link connects each SFC fabric port to one DLC fabric port. Each communication link includes cell-carrying lanes. Each fabric element of each SFC chassis collects per-lane statistics for each SFC fabric port of that SFC chassis. Each SFC chassis includes program code that obtains the per-lane statistics collected by the fabric element chip of that SFC chassis. A network element includes program code that gathers the per-lane statistics collected by each fabric element of each SFC chassis and integrates the statistics into a topology of the entire distributed fabric system.

Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Abstract: Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.

Abstract: A switch for a switching network includes a plurality of ports for communicating data traffic and a switch controller that controls switching between the plurality of ports. The switch controller selects a forwarding path for the data traffic based on at least topological congestion information for the switching network. In a preferred embodiment, the topological congestion information includes sFlow topological congestion information and the switch controller includes an sFlow client that receives the sFlow topological congestion information from an sFlow controller in the switching network.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: Systems and methods are provided for controlling a network switch. At least one forwarding element of the distributed switch is positioned at a first location of a network. A control element of the distributed switch is positioned at a second location of the network. The at least one forwarding element is controlled from the control element by establishing a communication between the forwarding element and the control element via the network.

Abstract: A switching network has a plurality of switches including at least a switch and a managing master switch. At the managing master switch, a first capability vector (CV) is received from the switch. The managing master switch determines whether the first CV is compatible with at least a second CV in a network membership data structure that records CVs of multiple switches in the switching network. In response to detecting an incompatibility, the managing master switch initiates an image update to an image of the switch. In response to a failure of the image update at the switch, the switch boots utilizing a mini-DC module that reestablishes communication between the switch with the managing master switch and retries the image update.

Abstract: A switching network has a plurality of switches including at least a switch and a managing master switch. At the managing master switch, a first capability vector (CV) is received from the switch. The managing master switch determines whether the first CV is compatible with at least a second CV in a network membership data structure that records CVs of multiple switches in the switching network. In response to detecting an incompatibility, the managing master switch initiates an image update to an image of the switch. In response to a failure of the image update at the switch, the switch boots utilizing a mini-DC module that reestablishes communication between the switch with the managing master switch and retries the image update.