Abstract: Each of first and second bridges of a data network having respective links to an external node implement a network bridge component that forwards traffic inside the data network and a virtual bridge component that forwards traffic outside of the data network. A virtual bridge is formed including the virtual bridge components of the first and second bridges and an interswitch link (ISL) between the virtual bridge components of the first and second bridges. Data frames are communicated with each of multiple external network nodes outside the data network via a respective one of multiple link aggregation groups all commonly supported by the virtual bridge.

Abstract: In one embodiment, a method for assigning a media access control (MAC) address includes receiving a request from a device for a MAC address at a port of a switching device, determining a MAC address to assign to the device based at least partially on the port, and responding to the request with the MAC address. In another embodiment, a method for retrieving a media access control (MAC) address includes sending a request for a MAC address to a MAC allocation server (MAAS), waiting a predetermined amount of time to receive a response to the request, wherein the response comprises the MAC address, and using the MAC address when the response to the request is received within the predetermined amount of time. Other systems, methods, and computer program products are presented according to more embodiments.

Abstract: Systems and methods are provided for overlaying a virtual network on a physical network in a data center environment. An overlay system is arranged in an overlay virtual network to include an overlay agent and an overlay helper. The overlay agent is implemented in an access switch. The overlay helper is implemented in an end station that is in communication with the access switch. Overlay parameters in compliance with an in-band protocol are transmitted between the overlay agent and the overlay helper.

Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

Abstract: A data handling system network includes a data handling system that is communicatively coupled to a switch by a network. The data handling system includes one or more logical partitions. Each logical partition includes a plurality of virtual switches and a plurality of virtual network interface cards. Each virtual network interface card is associated with a particular virtual switch and includes a plurality of QoS queues. The switch includes one or more switch partitions. Each switch partition includes a plurality of QoS queues that are associated with the QoS queues of the virtual network interface card. A packet is received with the virtual switch and the virtual switch sets and associates a QoS priority flag with the received packet. The virtual switch forwards the packet to a QoS queue comprised within the virtual network interface card based upon the QoS priority flag.

Abstract: Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: In one embodiment, an apparatus includes a memory, a hardware processor, and logic integrated with and/or executable by the processor. The logic is configured to receive one or more software defined network (SDN) routes dictating a path through a network comprising a plurality of devices. The logic is also configured to store the one or more SDN routes to the memory along with one or more traditional routes learned by the apparatus and/or configured by an administrator, and indicate the one or more SDN routes as being of a type different from the traditional routes. Moreover, the logic is configured to receive a priority ordering for a plurality of routes stored in the memory from the SDN controller, the plurality of routes including at least one SDN route, and construct a route information base (RIB) based on the plurality of routes and the priority ordering.

Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Abstract: In one embodiment, a system includes a network having a plurality of switches and one or more devices connected to one or more of the plurality of switches, a software defined network (SDN) controller connected to one or more of the plurality of switches in the network, the SDN controller having logic integrated with and/or executable by a processor, the logic being adapted to determine SDN routes through the network between the one or more devices and each of the plurality of switches and send one or more SDN routes to each switch in the network capable of communicating with the SDN controller. In other embodiments, methods and computer program products are also described for providing SDN routes through a network.

Abstract: A tool for assigning virtual port channels to one or more logical switch routers in a distributed system. The tool receives, by one or more computer processors, a request to assign a virtual port channel to a second logical switch router. The tool sends, by one or more computer processors, a request to negotiate a link-down on the channel on a first logical switch router to a universal fiber port on the first logical switch router for processing. The tool sends, by one or more computer processors, a request to create the channel on the second logical switch router to a second interface manager on the second logical switch router for processing. The tool sends, by one or more computer processors, a request to negotiate a link up on the channel on the second logical switch router to the universal fiber port on the first logical switch router for processing.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.

Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Abstract: Various aspects of the disclosed technology relate to techniques of creating test templates for test pattern generation. Residual test cubes for a plurality of faults are first generated based on a signal probability analysis of a circuit design. Test templates are then generated based on merging the residual test cubes. Finally, a plurality of test patterns and/or compressed test cubes are generated based on one of the test templates.

Abstract: In one embodiment, a system includes a server running a virtualization platform, the virtualization platform including logic adapted for creating one or more virtual machines (VMs) and logic adapted for managing a virtual switch (vSwitch), a controller in communication with the server, the controller including logic adapted for assigning a media access control (MAC) address and a virtual local area network (VLAN) identifier (ID) to each of the one or more VMs, wherein a specific tenant to which the one or more VMs belongs is indicated using a tenant ID derived from the VLAN ID, the MAC address, or a combination thereof. Other systems, methods, and computer program products are also described according to more embodiments.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.

Abstract: According to one embodiment, a system includes at least one switching distributed line card (DLC) configured to apply Access Control Lists (ACLs) on each switching interface of the at least one switching DLC to direct certain received packets to at least one appliance DLC to have deep packet inspection services performed on the certain received packets, and at least one central switch fabric coupler (SFC) in communication with the at least one switching DLC, where the at least one appliance DLC and the at least one switching DLC are connected to the at least one central SFC. Other systems, methods and computer program products for providing scalable virtual appliance cloud (SVAC) services are described in more embodiments.

Abstract: A system and method for a hybrid, variational, user-controlled, 3D mesh smoothing for orphaned shell meshes. The smoothing model is based on a variational combination of energy and equi-potential minimization theories. A variety of smoothing techniques for predicting a new location for the node-to-smooth are employed. Each node is moved according to a specific smoothing algorithm so as to keep element included angles, skew and distortion to a minimum. The variational smoother selection logic is based on nodal valency and element connectivity pattern of the node to smooth. Results show its consistency with both quadrilateral and quad-dominant meshes with a significant gain over conventional Laplacian schemes in terms of mesh quality, stability, user control and flexibility.

Abstract: A distributed fabric system has distributed line card (DLC) chassis and scaled-out fabric coupler (SFC) chassis. Each DLC chassis includes a network processor and fabric ports. Each network processor of each DLC chassis includes a fabric interface in communication with the DLC fabric ports of that DLC chassis. Each SFC chassis includes a fabric element and fabric ports. A communication link connects each SFC fabric port to one DLC fabric port. Each communication link includes cell-carrying lanes. Each fabric element of each SFC chassis collects per-lane statistics for each SFC fabric port of that SFC chassis. Each SFC chassis includes program code that obtains the per-lane statistics collected by the fabric element chip of that SFC chassis. A network element includes program code that gathers the per-lane statistics collected by each fabric element of each SFC chassis and integrates the statistics into a topology of the entire distributed fabric system.

Abstract: A switch for a switching network includes a plurality of ports for communicating data traffic and a switch controller that controls switching between the plurality of ports. The switch controller selects a forwarding path for the data traffic based on at least topological congestion information for the switching network. In a preferred embodiment, the topological congestion information includes sFlow topological congestion information and the switch controller includes an sFlow client that receives the sFlow topological congestion information from an sFlow controller in the switching network.