Patents by Inventor Niles Yang
Niles Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12585531Abstract: A maintenance system of a data storage device identifies which portions of the data storage device are more susceptible to data retention failures and other issues when compared with other portions of the data storage device. Various portions of the data storage device are identified as susceptible portions based on one or more characteristics. When the susceptible portions are identified, the maintenance system determines a frequency at which subsequent maintenance operations will be performed on the susceptible portions. The frequency may be based on the one or more characteristics, an amount of errors in data associated with the susceptible portion or a type of the susceptible portion.Type: GrantFiled: September 8, 2023Date of Patent: March 24, 2026Assignee: Sandisk Technologies, Inc.Inventors: Ramanathan Muthiah, Niles Yang, Daniel J. Linnen, Kirubakaran Periyannan
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Patent number: 12567475Abstract: A storage device may speed up error correction by pre-characterizing weak cell information in a memory device. The storage device includes a memory device with cells that may store multiple bits. A controller executes a pre-characterization operation on the memory device to identify a slow cell and/or a fast cell on the memory device. The controller retrieves weak cell information for the slow cell and/or the fast cell. The controller converts the weak cell information into values used by an error correction engine and provides the values to the error correction engine to be used in decoding information retrieved from the memory device.Type: GrantFiled: January 18, 2024Date of Patent: March 3, 2026Assignee: Sandisk Technologies, Inc.Inventors: Adam Jacobvitz, Piyush Dhotre, Niles Yang, Juan Carlos Lee, Eran Sharon, Idan Goldenberg, Zhenni Wan
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Patent number: 12566566Abstract: A storage device may ensure consistent performance when executing a read command provided by a host device. The storage device executes a read instruction received from the host device and executes a background operation to manage resources on a memory device and/or perform thermal throttling on the storage device. The storage device executes a formula including an interleave ratio to interleave host read operations with the background operation based on an operation time. The storage device also uses a read temperature threshold, a preset slowdown percentage, and/or a read speed to optimize host read operations during thermal throttling and thereby limit performance degradation during read operations.Type: GrantFiled: July 20, 2023Date of Patent: March 3, 2026Assignee: SANDISK TECHNOLOGIES, INC.Inventors: Niles Yang, Daniel J Linnen, Piyush Dhotre, Adam Jacobvitz
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Patent number: 12536104Abstract: A stream classification system of a data storage device monitors an access frequency of data stored by the data storage device. If the data is classified as cold data, the stream classification system rewrites the cold data to a primary storage partition using one or more special data storage parameters. The one or more special data storage parameters cause the cold data to be more resilient to various data storage issues including, but not limited to, data retention issues, read disturb issues and/or temperature cross issues.Type: GrantFiled: January 11, 2024Date of Patent: January 27, 2026Assignee: Sandisk Technologies, Inc.Inventors: Piyush A. Dhotre, Leeladhar Agarwal, Adam Noah Jacobvitz, Niles Yang
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Patent number: 12488854Abstract: In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to: receive, from a host, a command to read data from the memory, wherein the command comprises a data integrity level threshold; read the data from the memory; determine a data integrity level of the data; in response to the data integrity level of the data being above the threshold, send the data to the host; and in response to the data integrity level of the data not being above the threshold: perform at least one iteration of an error correction operation on the data until the data integrity level of the data is above the threshold; and send the data to the host. Other embodiments are provided, and each of the embodiments can be used alone or in combination.Type: GrantFiled: July 26, 2023Date of Patent: December 2, 2025Assignee: Western Digital Technologies, Inc.Inventors: Niles Yang, Judah Gamliel Hahn
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Patent number: 12449986Abstract: A storage device manages the effects of read operations on the power consumption on the storage device. A controller on the storage device determines the openness of blocks on a memory device. The controller may execute a first protocol and/or a second protocol. In executing the first protocol, the controller may fill open blocks on the memory device such that subsequent read operations are performed on blocks that have been filled. In executing the second protocol, the controller may control which read operations are sent to the memory device based on real-time power consumption on the storage device.Type: GrantFiled: December 8, 2023Date of Patent: October 21, 2025Assignee: SANDISK TECHNOLOGIES, INC.Inventors: Adam Jacobvitz, Piyush Dhotre, Niles Yang, Brandon Jensen
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Publication number: 20250239317Abstract: A storage device may speed up error correction by pre-characterizing weak cell information in a memory device. The storage device includes a memory device with cells that may store multiple bits. A controller executes a pre-characterization operation on the memory device to identify a slow cell and/or a fast cell on the memory device. The controller retrieves weak cell information for the slow cell and/or the fast cell. The controller converts the weak cell information into values used by an error correction engine and provides the values to the error correction engine to be used in decoding information retrieved from the memory device.Type: ApplicationFiled: January 18, 2024Publication date: July 24, 2025Applicant: SanDisk Technologies LLCInventors: ADAM JACOBVITZ, PIYUSH DHOTRE, NILES YANG, JUAN CARLOS LEE, ERAN SHARON, IDAN GOLDENBERG, ZHENNI WAN
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Publication number: 20250231884Abstract: A stream classification system of a data storage device monitors an access frequency of data stored by the data storage device. If the data is classified as cold data, the stream classification system rewrites the cold data to a primary storage partition using one or more special data storage parameters. The one or more special data storage parameters cause the cold data to be more resilient to various data storage issues including, but not limited to, data retention issues, read disturb issues and/or temperature cross issues.Type: ApplicationFiled: January 11, 2024Publication date: July 17, 2025Inventors: Piyush A. Dhotre, Leeladhar Agarwal, Adam Noah Jacobvitz, Niles Yang
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Patent number: 12353709Abstract: A storage device is communicatively coupled to a host that defines a quality of service level for responses transmitted from the storage device to the host. The storage device includes a memory device to store data. The storage device also includes a controller to perform background operations to manage resources on the memory device while performing foreground operations according to the quality of service level set by the host. The controller generates a free block file including information on free blocks in the memory device and transmits the free block file to the host. The host uses the free block file to determine when the memory device is at or near a critical level of block availability and transmits an indication from to the controller. The controller adjusts the priority of the background operations in response to receipt of the indication to maintain the quality of service level.Type: GrantFiled: August 9, 2023Date of Patent: July 8, 2025Assignee: Sandisk, Inc.Inventor: Niles Yang
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Publication number: 20250190124Abstract: A storage device manages the effects of read operations on the power consumption on the storage device. A controller on the storage device determines the openness of blocks on a memory device. The controller may execute a first protocol and/or a second protocol. In executing the first protocol, the controller may fill open blocks on the memory device such that subsequent read operations are performed on blocks that have been filled. In executing the second protocol, the controller may control which read operations are sent to the memory device based on real-time power consumption on the storage device.Type: ApplicationFiled: December 8, 2023Publication date: June 12, 2025Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: ADAM JACOBVITZ, PIYUSH DHOTRE, NILES YANG, BRANDON JENSEN
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Patent number: 12265733Abstract: Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better quality of service while substantially maintaining acceptable levels of other pertinent performance characteristics. In some examples, a sequence of host read-modify-write commands is handled by generating a copy of implicated subfiles in a data buffer, applying subfile updates to the copy in the data buffer in accordance with the sequence, and relocating the implicated subfiles in the NAND memory using the updated versions thereof from the data buffer.Type: GrantFiled: August 14, 2023Date of Patent: April 1, 2025Assignee: Sandisk Technologies, Inc.Inventors: Niles Yang, Daniel J. Linnen, Judah Gamliel Hahn
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Publication number: 20250086048Abstract: A maintenance system of a data storage device identifies which portions of the data storage device are more susceptible to data retention failures and other issues when compared with other portions of the data storage device. Various portions of the data storage device are identified as susceptible portions based on one or more characteristics. When the susceptible portions are identified, the maintenance system determines a frequency at which subsequent maintenance operations will be performed on the susceptible portions. The frequency may be based on the one or more characteristics, an amount of errors in data associated with the susceptible portion or a type of the susceptible portion.Type: ApplicationFiled: September 8, 2023Publication date: March 13, 2025Inventors: Ramanathan Muthiah, Niles Yang, Daniel J. Linnen, Kirubakaran Periyannan
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Patent number: 12248397Abstract: Methods for recording commands in memory and providing the recorded commands. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, a controller memory including a storage firmware and a record mapping table, and a processor. The processor, when executing the storage firmware, is configured to receive a record identifier, receive a command including data to be stored in the memory, and create an entry in the record mapping table associating the record identifier with a logical block address of the command. The command is received after the record identifier. The processor may receive a playback identifier that includes the record identifier and determine, using the record mapping table, a location of the associated command in the memory. The command is provided to an external device.Type: GrantFiled: July 28, 2023Date of Patent: March 11, 2025Assignee: Sandisk Technologies, Inc.Inventors: Daniel J. Linnen, Ramanathan Muthiah, Niles Yang, Judah Gamliel Hahn, Mark Shlick
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Publication number: 20250036564Abstract: Methods for recording commands in memory and providing the recorded commands. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, a controller memory including a storage firmware and a record mapping table, and a processor. The processor, when executing the storage firmware, is configured to receive a record identifier, receive a command including data to be stored in the memory, and create an entry in the record mapping table associating the record identifier with a logical block address of the command. The command is received after the record identifier. The processor may receive a playback identifier that includes the record identifier and determine, using the record mapping table, a location of the associated command in the memory. The command is provided to an external device.Type: ApplicationFiled: July 28, 2023Publication date: January 30, 2025Inventors: Daniel J. Linnen, Ramanathan Muthiah, Niles Yang, Judah Gamliel Hahn, Mark Shlick
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Publication number: 20250028475Abstract: A storage device may ensure consistent performance when executing a read command provided by a host device. The storage device executes a read instruction received from the host device and executes a background operation to manage resources on a memory device and/or perform thermal throttling on the storage device. The storage device executes a formula including an interleave ratio to interleave host read operations with the background operation based on an operation time. The storage device also uses a read temperature threshold, a preset slowdown percentage, and/or a read speed to optimize host read operations during thermal throttling and thereby limit performance degradation during read operations.Type: ApplicationFiled: July 20, 2023Publication date: January 23, 2025Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: NILES YANG, DANIEL J LINNEN, PIYUSH DHOTRE, ADAM JACOBVITZ
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Publication number: 20240420791Abstract: In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to: receive, from a host, a command to read data from the memory, wherein the command comprises a data integrity level threshold; read the data from the memory; determine a data integrity level of the data; in response to the data integrity level of the data being above the threshold, send the data to the host; and in response to the data integrity level of the data not being above the threshold: perform at least one iteration of an error correction operation on the data until the data integrity level of the data is above the threshold; and send the data to the host. Other embodiments are provided, and each of the embodiments can be used alone or in combination.Type: ApplicationFiled: July 26, 2023Publication date: December 19, 2024Applicant: Western Digital Technologies, Inc.Inventors: Niles Yang, Judah Gamliel Hahn
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Publication number: 20240404994Abstract: A thermally conductive spacer is positioned between two semiconductor dies in a stack of semiconductor dies. The spacer includes thermal conductivity features that dissipate heat or otherwise conduct heat away from the semiconductor dies in the stack. The spacer may have dimensions that are larger than the dimensions of the semiconductor dies in the stack. The thermal conductivity features of the spacer, in addition to the larger dimensions, enable the spacer to effectively dissipate heat from, and improve a thermal profile of, the stack of semiconductor dies.Type: ApplicationFiled: July 26, 2023Publication date: December 5, 2024Inventors: Jayavel Pachamuthu, Niles Yang, Daniel J. Linnen, Kirubakaran Periyannan
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Publication number: 20240302957Abstract: A storage device is communicatively coupled to a host that defines a quality of service level for responses transmitted from the storage device to the host. The storage device includes a memory device to store data. The storage device also includes a controller to perform background operations to manage resources on the memory device while performing foreground operations according to the quality of service level set by the host. The controller generates a free block file including information on free blocks in the memory device and transmits the free block file to the host. The host uses the free block file to determine when the memory device is at or near a critical level of block availability and transmits an indication from to the controller. The controller adjusts the priority of the background operations in response to receipt of the indication to maintain the quality of service level.Type: ApplicationFiled: August 9, 2023Publication date: September 12, 2024Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventor: Niles Yang
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Publication number: 20240192886Abstract: Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better quality of service while substantially maintaining acceptable levels of other pertinent performance characteristics. In some examples, a sequence of host read-modify-write commands is handled by generating a copy of implicated subfiles in a data buffer, applying subfile updates to the copy in the data buffer in accordance with the sequence, and relocating the implicated subfiles in the NAND memory using the updated versions thereof from the data buffer.Type: ApplicationFiled: August 14, 2023Publication date: June 13, 2024Inventors: Niles Yang, Daniel J. Linnen, Judah Gamliel Hahn
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Patent number: 11941269Abstract: A data storage device includes a non-volatile memory device having one or more memory dies and each of the memory dies include a plurality of input-output (I/O) lines. The data storage device further includes a controller. The controller is configured to receive an instruction to enter a low-power operating mode. Entering the low-power operating mode includes removing power from the one or more memory dies, providing an output signal toggling between a logic high and a logic low at a predetermined frequency to the plurality of I/O lines for a predetermined period of time, and operating in the low-power operating mode upon the expiration of the predetermined period of time.Type: GrantFiled: March 22, 2022Date of Patent: March 26, 2024Assignee: Western Digital Technologies, Inc.Inventors: Niles Yang, Sahil Sharma, Phil D. Reusswig