Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Abstract: Improving performance of a read in a memory system. Various methods include: reading data from a word line in a memory block, where during the read, associated parameters are generated that include: a value indicative of a throughput time, and a value indicative of a bit error rate (BER); retrieving the value indicative of the throughput time and the value indicative of the BER; and performing a read improvement process if the value indicative of the throughput time is above a threshold value. The method also includes performing the read improvement process by: flagging the memory block if the value indicative of the BER is at or below and expected BER; and performing cleanup operations if the value indicative of the BER is higher than the expected BER.

Abstract: For solid state drive (SSD) or other memory system formed of multiple memory dies, techniques are presented for operation in a standby mode with increased power savings. The memory dies are operable in a regular standby mode and in a low power standby mode. Based upon the amount of current each of the memory dies in the regular standby mode, when the device goes into standby the memory dies that draw higher amounts of current when in the regular standby mode are instead placed into the low power standby mode. The amount of current drawn by each of the memory die in the regular standby mode can be determined for each of the memory dies at die sort or as part of the memory test process, or can be determine by an assembled SSD itself.

Abstract: A storage system comprises a controller connected to blocks of non-volatile memory cells. The memory cells can be operated as single level cell (“SLC”) memory cells or multi-level cell (“MLC”) memory cells. To increase write performance for a subset of memory cells being operated as SLC memory cells, the controller performs a deeper erase process and a weaker program process for the subset of memory cells. The weaker program process results in a programmed threshold voltage distribution that is lower than the “nominal” programmed threshold voltage distribution. Having a lower programmed threshold voltage distribution reduces the magnitude of the programming and sensing voltages needed and, therefore, shortens the time required to generate the programming and sensing voltages, and reduces power consumption.

Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

Abstract: Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.

Abstract: In one embodiment, there is a method for implementing balancing block wearing leveling at a storage device including one or more single level cell (SLC) blocks in a SLC block pool and one or more non-single level cell (nSLC) blocks in a nSLC block pool for storing data and a memory controller for performing operations on the SLC blocks and nSLC blocks, the method comprising: at the memory controller: receiving a first request to perform a wear leveling operation on a respective block pool of one of: the SLC block pool and the nSLC block pool; determining whether one or more blocks in the respective block pool meet block pool transfer criteria; in response to a determination that the one or more blocks in the respective block pool meets block pool transfer criteria, reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool; and in response to a determination that the one or more blocks in the respective block pool does not meet block pool trans

Abstract: A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.

Abstract: Detecting a faulty memory block. Various methods include: performing a read operation on a memory block of the memory array, the read operation generates a failed bit count; determining the failed bit count in above a value associated with an overall failed bit count; determining the failed bit count is above a threshold value; in response, performing a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, the confirmation process results in erase pass or erase fail; and marking the memory block for garbage collection in response to determining the confirmation process results in erase fail. Methods additionally include setting the level of the erase cycle by modifying at least one selected form the group comprising: an erase voltage parameter; an erase verify parameter; and a number of bits ignored during the erase cycle.

Abstract: Recovering data from a faulty memory block in a memory system. Various methods include: reading a target word line in a memory block to obtain a first data; determining the first data has an uncorrectable error; and then adjust bias parameters of a first group of neighboring word lines within the memory block, where adjusting bias parameters creates a first adjusted bias parameters; and reading the target word line using the adjusted bias parameters to obtain second data from the target word line. The method also includes determining the second data has a second uncorrectable error; and then adjusting bias parameters of a second group of lines within the memory block, where adjusting the bias parameters of the second group creates second adjusted bias parameters; and reading the target word line using the first and second adjusted bias parameters to obtain a third data from the target word line.

Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

Abstract: An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.

Abstract: In one embodiment, there is a method for implementing balancing block wearing leveling at a storage device including one or more single level cell (SLC) blocks in a SLC block pool and one or more non-single level cell (nSLC) blocks in a nSLC block pool for storing data and a memory controller for performing operations on the SLC blocks and nSLC blocks, the method comprising: at the memory controller: receiving a first request to perform a wear leveling operation on a respective block pool of one of: the SLC block pool and the nSLC block pool; determining whether one or more blocks in the respective block pool meet block pool transfer criteria; in response to a determination that the one or more blocks in the respective block pool meets block pool transfer criteria, reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool; and in response to a determination that the one or more blocks in the respective block pool does not meet block pool trans

Abstract: Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.

Abstract: A storage system and method for performing high-speed read and write operations are disclosed. In general, these embodiments discuss ways for performing a fast read in response to determining that the fast read will probably not have a negative impact on performance due to error correction and performing a fast write in response to determining that a storage system criterion is satisfied.

Abstract: A method is provided that includes performing a post-write read operation on a block of memory cells that includes a select gate transistor, and based on results of the post-write read operation selectively performing a select gate maintenance operation on the select gate transistor.