Patents by Inventor Niloy Mukherjee

Niloy Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200306423
    Abstract: A wound monitoring system including a sensor for detecting color and flow rate of a fluid flowing through a wound drain tubing, a base station for receiving color and flow rate data from the sensor over the one or more networks, for storing the data, and for sending notifications over the one or more networks, and a user device for receiving the notification over the one or more networks. Also disclosed is a wound monitoring system that includes the sensor, the base station, a cloud server, and the user device. The base station receives the data from the sensor and transmits the data over one or more networks to the cloud server. Further disclosed is a wound drain monitoring method that employs the wound monitoring system.
    Type: Application
    Filed: February 28, 2020
    Publication date: October 1, 2020
    Inventors: Nikin Tharan, Indraneil Mukherjee, Niloy Choudhury, Max Narovlyansky
  • Patent number: 10784170
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Patent number: 10756198
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 10748602
    Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Huichu Liu, Sasikanth Manipatruni, Daniel H. Morris, Kaushik Vaidyanathan, Niloy Mukherjee, Dmitri E. Nikonov, Ian Young, Tanay Karnik
  • Patent number: 10727339
    Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Gilbert Dewey, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Ravi Pillarisetty, Han Wui Then, Niloy Mukherjee, Sansaptak Dasgupta
  • Patent number: 10706921
    Abstract: One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 7, 2020
    Assignee: INTEL CORPORATION
    Inventors: Elijah V. Karpov, Ravi Pillarisetty, Prashant Majhi, Niloy Mukherjee, Uday Shah
  • Publication number: 20200203604
    Abstract: Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal and an electrolyte; wherein the electrolyte is coupled between the active metal and the source/drain region when the transistor is an n-type metal oxide semiconductor (NMOS) transistor, and the active metal is coupled between the electrolyte and the source/drain region when the transistor is a p-type metal oxide semiconductor (PMOS) transistor.
    Type: Application
    Filed: September 25, 2016
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Elijah V. Karpov, Prashant Majhi, Niloy Mukherjee
  • Patent number: 10693008
    Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Marko Radosavljevic, Jack T. Kavalieros, Ravi Pillarisetty, Niti Goel, Van H. Le, Gilbert Dewey, Benjamin Chu-Kung
  • Patent number: 10658586
    Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: James S. Clarke, Ravi Pillarisetty, Uday Shah, Tejaswi K. Indukuri, Niloy Mukherjee, Elijah V. Karpov, Prashant Majhi
  • Patent number: 10658471
    Abstract: Described herein are methods and structures integrating one or more TMDC crystal heteroepitaxially grown on one or more group III-Nitride (III-N) crystal. The TMDC crystal may be grown on a III-N heteroepitaxial crystal that has been grown on crystalline silicon substrate. One or more of III-N devices and silicon devices employing separated regions of the heteroepitaxial substrate may be integrated with a TMDC device fabricated on with the TMDC crystal. In some embodiments, impurity-doped III-N source/drain regions provide a low resistance coupling between metallization and a TMDC-channeled transistor.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Ravi Pillarisetty
  • Publication number: 20200144362
    Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
    Type: Application
    Filed: December 9, 2019
    Publication date: May 7, 2020
    Applicant: INTEL CORPORATION
    Inventors: Anand S. MURTHY, Glenn A. GLASS, Tahir GHANI, Ravi PILLARISETTY, Niloy MUKHERJEE, Jack T. KAVALIEROS, Roza KOTLYAR, Willy RACHMADY, Mark Y. LIU
  • Publication number: 20200133950
    Abstract: Techniques are described herein for executing queries on distinct portions of a database object that has been separate into chunks and distributed across the volatile memories of a plurality of nodes in a clustered database system. The techniques involve redistributing the in-memory database object portions on changes to the clustered database system. Each node may maintain a mapping indicating which nodes in the clustered database system store which chunks, and timestamps indicating when each mapping entry was created or updated. A query coordinator may use the timestamps to select a database server instance with local in memory access to data required by a portion of a query to process that portion of the query.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: NILOY MUKHERJEE, KARTIK KULKARNI, TIRTHANKAR LAHIRI, VINEET MARWAH, JUAN LOAIZA
  • Patent number: 10630716
    Abstract: A novel enterprise security solution allows for precise interception and surgical response to attack progression, in real time, as it occurs across a distributed infrastructure. The solution includes a data monitoring and management framework that continually models system level host and network activities as mutually exclusive infrastructure wide execution sequences and bucketizes them into unique execution trails. A multimodal intelligent security middleware detects indicators of compromise in real-time on top of subsets of each unique execution trail using rule based behavioral analytics, machine learning based anomaly detection, and other sources. Each detection result dynamically contributes to aggregated risk scores at execution trail level granularities. These scores can be used to prioritize and identify highest risk attack trails to end users, along with steps that such end users can perform to mitigate further damage and progression of an attack.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 21, 2020
    Assignee: Confluera, Inc.
    Inventors: Abhijit Ghosh, Niloy Mukherjee, Eun-Gyu Kim
  • Patent number: 10630715
    Abstract: A novel enterprise security solution allows for precise interception and surgical response to attack progression, in real time, as it occurs across a distributed infrastructure. The solution includes a data monitoring and management framework that continually models system level host and network activities as mutually exclusive infrastructure wide execution sequences and bucketizes them into unique execution trails. A multimodal intelligent security middleware detects indicators of compromise in real-time on top of subsets of each unique execution trail using rule based behavioral analytics, machine learning based anomaly detection, and other sources. Each detection result dynamically contributes to aggregated risk scores at execution trail level granularities. These scores can be used to prioritize and identify highest risk attack trails to end users, along with steps that such end users can perform to mitigate further damage and progression of an attack.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 21, 2020
    Assignee: Confluera, Inc.
    Inventors: Abhijit Ghosh, Niloy Mukherjee, Eun-Gyu Kim
  • Patent number: 10630703
    Abstract: A novel enterprise security solution allows for precise interception and surgical response to attack progression, in real time, as it occurs across a distributed infrastructure. The solution includes a data monitoring and management framework that continually models system level host and network activities as mutually exclusive infrastructure wide execution sequences and bucketizes them into unique execution trails. A multimodal intelligent security middleware detects indicators of compromise in real-time on top of subsets of each unique execution trail using rule based behavioral analytics, machine learning based anomaly detection, and other sources. Each detection result dynamically contributes to aggregated risk scores at execution trail level granularities. These scores can be used to prioritize and identify highest risk attack trails to end users, along with steps that such end users can perform to mitigate further damage and progression of an attack.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 21, 2020
    Assignee: Confluera, Inc.
    Inventors: Abhijit Ghosh, Niloy Mukherjee, Eun-Gyu Kim
  • Patent number: 10630704
    Abstract: A novel enterprise security solution allows for precise interception and surgical response to attack progression, in real time, as it occurs across a distributed infrastructure. The solution includes a data monitoring and management framework that continually models system level host and network activities as mutually exclusive infrastructure wide execution sequences and bucketizes them into unique execution trails. A multimodal intelligent security middleware detects indicators of compromise in real-time on top of subsets of each unique execution trail using rule based behavioral analytics, machine learning based anomaly detection, and other sources. Each detection result dynamically contributes to aggregated risk scores at execution trail level granularities. These scores can be used to prioritize and identify highest risk attack trails to end users, along with steps that such end users can perform to mitigate further damage and progression of an attack.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 21, 2020
    Assignee: Confluera, Inc.
    Inventors: Abhijit Ghosh, Niloy Mukherjee, Eun-Gyu Kim
  • Patent number: 10572469
    Abstract: Techniques for non-disruptive versioning of in-memory units in a database are provided. A database server generates and maintains a first IMU that reflects changes made to a mirrored-data-set up to a first snapshot time, and a second IMU that reflects changes made to the mirrored-data-set up to a second snapshot time. During a first period, the database server responds to updates to first data items in the mirrored data by storing first staleness metadata that indicates that the copies of the first data items in the first IMU are stale. During a second period, the database server responds to updates to second data items in the mirrored data by storing second staleness metadata that indicates that the copies of the second data items in the second IMU are stale. The database server responds to a request by accessing the first IMU or the second IMU.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 25, 2020
    Assignee: Oracle International Corporation
    Inventors: Atrayee Mullick, Niloy Mukherjee, Sanket Hase, Tirthankar Lahiri, Juan Loaiza
  • Patent number: 10573717
    Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Niti Goel, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 10574683
    Abstract: A novel enterprise security solution allows for precise interception and surgical response to attack progression, in real time, as it occurs across a distributed infrastructure. The solution includes a data monitoring and management framework that continually models system level host and network activities as mutually exclusive infrastructure wide execution sequences and bucketizes them into unique execution trails. A multimodal intelligent security middleware detects indicators of compromise in real-time on top of subsets of each unique execution trail using rule based behavioral analytics, machine learning based anomaly detection, and other sources. Each detection result dynamically contributes to aggregated risk scores at execution trail level granularities. These scores can be used to prioritize and identify highest risk attack trails to end users, along with steps that such end users can perform to mitigate further damage and progression of an attack.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: February 25, 2020
    Assignee: Confluera, Inc.
    Inventors: Abhijit Ghosh, Niloy Mukherjee, Eun-Gyu Kim
  • Patent number: 10573809
    Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Ravi Pillarisetty, Uday Shah, Elijah V. Karpov, Niloy Mukherjee, Pulkit Jain, Aravind S. Killampalli, Jay P. Gupta, James S. Clarke