Patents by Inventor Niloy Mukherjee

Niloy Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10439134
    Abstract: Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: October 8, 2019
    Assignee: INTEL CORPORATION
    Inventors: Prashant Majhi, Elijah V. Karpov, Uday Shah, Niloy Mukherjee, Charles C. Kuo, Ravi Pillarisetty, Brian S. Doyle, Robert S. Chau
  • Patent number: 10424620
    Abstract: A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: September 24, 2019
    Assignee: INTEL CORPORATION
    Inventors: Prashant Majhi, Elijah V. Karpov, Ravi Pillarisetty, Uday Shah, Niloy Mukherjee
  • Patent number: 10396211
    Abstract: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Roza Kotlyar, Niloy Mukherjee, Charles C. Kuo, Uday Shah, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 10388869
    Abstract: Thin film resistive memory material stacks including at least one of a high work function metal oxide at an interface of a first electrode and a thin film memory material, and a low work function rare earth metal at an interface of a second electrode and the thin film memory material. The high work function metal oxide provides a good Schottky barrier height relative to memory material for high on/off current ratio. Compatibility of the metal oxide with switching oxide reduces cycling loss of oxygen/vacancies for improved memory device durability. The low work function rare earth metal provides high oxygen solubility to enhance vacancy creation within the memory material in as-deposited state for low forming voltage requirements while providing an ohmic contact to the resistive memory material.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Elijah V. Karpov, Niloy Mukherjee, Ravi Pillarisetty, Uday Shah, Brian S. Doyle, Robert S. Chau
  • Publication number: 20190244936
    Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Han Wui THEN, Robert CHAU, Valluri RAO, Niloy MUKHERJEE, Marko RADOSAVLJEVIC, Ravi PILLARISETTY, Gilbert DEWEY, Jack KAVALIEROS
  • Publication number: 20190229022
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Inventors: Marko RADOSAVLJEVIC, Ravi PILLARISETTY, Gilbert DEWEY, Niloy MUKHERJEE, Jack KAVALIEROS, Willy RACHMADY, Van LE, Benjamin CHU-KUNG, Matthew METZ, Robert CHAU
  • Patent number: 10355205
    Abstract: Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Ravi Pillarisetty, Niloy Mukherjee, Uday Shah, Elijah V. Karpov, Brian S. Doyle, Robert S. Chau
  • Publication number: 20190214559
    Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.
    Type: Application
    Filed: July 2, 2016
    Publication date: July 11, 2019
    Inventors: James S. CLARKE, Ravi PILLARISETTY, Uday SHAH, Tejaswi K. INDUKURI, Niloy MUKHERJEE, Elijah V. KARPOV, Prashant MAJHI
  • Publication number: 20190214433
    Abstract: Disclosed herein are asymmetric selectors for memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a storage element; and a selector device coupled to the storage element, wherein the selector device has a positive threshold voltage and a negative threshold voltage, and a magnitude of the positive threshold voltage is different from a magnitude of the negative threshold voltage.
    Type: Application
    Filed: September 24, 2016
    Publication date: July 11, 2019
    Applicant: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Ravi Pillarisetty, Niloy Mukherjee
  • Patent number: 10340443
    Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Kaan Oguz, Kevin P. O'Brien, David L. Kencke, Elijah V. Karpov, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, Robert S. Chau, Niloy Mukherjee, Prashant Majhi
  • Patent number: 10340275
    Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Jack T. Kavalieros, Robert S. Chau, Niloy Mukherjee, Rafael Rios, Prashant Majhi, Van H. Le, Ravi Pillarisetty, Uday Shah, Gilbert Dewey, Marko Radosavljevic
  • Publication number: 20190198100
    Abstract: Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a top electrode, a modulated interfacial region, and a bottom electrode. The thickness of the modulated interfacial region can be modulated between an on state thickness and an off state thickness and the bottom electrode is an active electrode that is a source for metal ions for the creation of a filament between the top electrode and the bottom electrode. In an example, the filament is created when the transistor is in an on state and the filament is not present when the transistor is in an off state.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov, Niloy Mukherjee, James S. Clarke
  • Patent number: 10319646
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Publication number: 20190165106
    Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 30, 2019
    Inventors: Han Wui THEN, Robert CHAU, Benjamin CHU-KUNG, Gilbert DEWEY, Jack KAVALIEROS, Matthew METZ, Niloy MUKHERJEE, Ravi PILLARISETTY, Marko RADOSAVLJEVIC
  • Patent number: 10290614
    Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Valluri Rao, Niloy Mukherjee, Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Jack Kavalieros
  • Patent number: 10275184
    Abstract: Techniques are described herein for executing queries on distinct portions of a database object that has been separate into chunks and distributed across the volatile memories of a plurality of nodes in a clustered database system. The techniques involve receiving a query that requires work to be performed on data that resides in a plurality of on disk extents. A parallel query coordinator that is aware of the in-memory distribution divides the work into granules that align with the in-memory separation. The parallel query coordinator then sends each granule to the database server instance with local in memory access to the data required by the granule and aggregates the results to respond to the query.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: April 30, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Niloy Mukherjee, Vineet Marwah, Hui Jin, Kartik Kulkarni
  • Patent number: 10263074
    Abstract: Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Patent number: 10249490
    Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz, Niloy Mukherjee, Nancy M. Zelick, Gilbert Dewey, Willy Rachmady, Marko Radosavljevic, Van H. Le, Ravi Pillarisetty, Sansaptak Dasgupta
  • Publication number: 20190088747
    Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.
    Type: Application
    Filed: November 21, 2018
    Publication date: March 21, 2019
    Inventors: Niti GOEL, Gilbert DEWEY, Niloy MUKHERJEE, Matthew V. METZ, Marko RADOSAVLIJEVIC, Benjamin CHU-KUNG, Jack T. KAVALIEROS, Robert S. CHAU
  • Patent number: 10236369
    Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung, Marko Radosavljevic, Niloy Mukherjee, Gilbert Dewey, Been Y. Jin, Robert S. Chau