Patents by Inventor Niloy Mukherjee

Niloy Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167216
    Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Publication number: 20210125849
    Abstract: The disclosed technology generally relates to semiconductor processing and more particularly to placing a substrate in a semiconductor manufacturing equipment for processing, and to apparatuses for placing the substrate in the semiconductor manufacturing equipment. In one aspect, a method of calibrating a process position of a semiconductor substrate in a process chamber comprises securing a calibration substrate on a susceptor in a processing chamber under an open chamber condition using a securing device, wherein securing comprises preventing the substrate from sliding laterally on the susceptor by more than a predefined tolerance from a centered position relative to a susceptor center. The method additionally comprises subjecting the calibration substrate under a process condition different from the open chamber condition. The method additionally comprises transferring the calibration substrate from the susceptor using a robot arm.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Inventors: Alex Finkelman, Somilkumar J. Rathi, Niloy Mukherjee
  • Publication number: 20210104397
    Abstract: The disclosed technology generally relates to forming a titanium nitride layer, and more particularly to forming by atomic layer deposition a titanium nitride layer on a seed layer. In one aspect, a semiconductor structure comprises a semiconductor substrate comprising a non-metallic surface. The semiconductor structure additionally comprises a seed layer comprising silicon (Si) and nitrogen (N) conformally coating the non-metallic surface and a TiN layer conformally coating the seed layer. Aspects are also directed to methods of forming the semiconductor structures.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Sung-Hoon Jung, Niloy Mukherjee, Hee Seok Kim, Kyu Jin Choi, Moonsig Joo, Hae Young Kim, Yoshikazu Okuyama, Nariman Naghibolashrafi, Bunsen B. Nie, Somilkumar J. Rathi
  • Publication number: 20210104665
    Abstract: The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for nonvolatile memory devices, and methods of forming the same. In one aspect, a method of forming an electrode for a phase change memory device comprises forming over a semiconductor substrate an electrode comprising titanium silicon nitride (TiSiN) on a phase change storage element configured to store a memory state. Forming the electrode comprises exposing a semiconductor substrate to one or more cyclical vapor deposition cycles, wherein a plurality of the cyclical vapor deposition cycles comprises an exposure to a Ti precursor, an exposure to a N precursor and an exposure to a Si precursor.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Jae Seok Heo, Jerry Mack, Somilkumar J. Rathi, Niloy Mukherjee
  • Publication number: 20210104396
    Abstract: The disclosed technology generally relates to forming a thin film comprising titanium nitride (TiN), and more particularly to forming by a cyclical vapor deposition process the thin film comprising (TiN).
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Sung-Hoon Jung, Niloy Mukherjee, Yoshikazu Okuyama, Nariman Naghibolashrafi, Bunsen B. Nie, Hae Young Kim, Somilkumar J. Rathi
  • Publication number: 20210104433
    Abstract: The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Niloy Mukherjee, Hae Young Kim, Jerry Mack, Jae Seok Heo, Sung-Hoon Jung, Somilkumar J. Rathi, Srishti Chugh, Nariman Naghibolashrafi, Yoshikazu Okuyama, Bunsen B. Nie
  • Patent number: 10950733
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 16, 2021
    Assignee: Google LLC
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10910436
    Abstract: Disclosed herein are asymmetric selectors for memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a storage element; and a selector device coupled to the storage element, wherein the selector device has a positive threshold voltage and a negative threshold voltage, and a magnitude of the positive threshold voltage is different from a magnitude of the negative threshold voltage.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Prashant Majhi, Ravi Pillarisetty, Niloy Mukherjee
  • Patent number: 10897009
    Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Ravi Pillarisetty, Prashant Majhi, Uday Shah, Ryan E Arch, Markus Kuhn, Justin S. Brockman, Huiying Liu, Elijah V Karpov, Kaan Oguz, Brian S. Doyle, Robert S. Chau
  • Patent number: 10887337
    Abstract: Infrastructure attacks involving lateral movement are identified by monitoring system level activities using software agents deployed on respective operating systems, and constructing, based on the system level activities, an execution graph comprising execution trails. A logon session between a remote connection client executing on a first operating system and a remote connection server executing on a second operating system is identified. Behavior exhibited from the logon session is attributed to a first global execution trail in the execution graph. A reconnection to the logon session between a remote connection client executing on a third operating system and the remote connection server is then identified, and, thereafter, behavior exhibited from the logon session is attributed to a second global execution trail in the execution graph.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: January 5, 2021
    Assignee: Confluera, Inc.
    Inventors: Eun-Gyu Kim, Rushikesh Patil, Sandeep Siroya, Niloy Mukherjee
  • Patent number: 10784170
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Patent number: 10756198
    Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
  • Patent number: 10748602
    Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Huichu Liu, Sasikanth Manipatruni, Daniel H. Morris, Kaushik Vaidyanathan, Niloy Mukherjee, Dmitri E. Nikonov, Ian Young, Tanay Karnik
  • Patent number: 10727339
    Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Gilbert Dewey, Van H. Le, Jack T. Kavalieros, Marko Radosavljevic, Ravi Pillarisetty, Han Wui Then, Niloy Mukherjee, Sansaptak Dasgupta
  • Patent number: 10706921
    Abstract: One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 7, 2020
    Assignee: INTEL CORPORATION
    Inventors: Elijah V. Karpov, Ravi Pillarisetty, Prashant Majhi, Niloy Mukherjee, Uday Shah
  • Publication number: 20200203604
    Abstract: Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal and an electrolyte; wherein the electrolyte is coupled between the active metal and the source/drain region when the transistor is an n-type metal oxide semiconductor (NMOS) transistor, and the active metal is coupled between the electrolyte and the source/drain region when the transistor is a p-type metal oxide semiconductor (PMOS) transistor.
    Type: Application
    Filed: September 25, 2016
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Elijah V. Karpov, Prashant Majhi, Niloy Mukherjee
  • Patent number: 10693008
    Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Marko Radosavljevic, Jack T. Kavalieros, Ravi Pillarisetty, Niti Goel, Van H. Le, Gilbert Dewey, Benjamin Chu-Kung
  • Patent number: 10658471
    Abstract: Described herein are methods and structures integrating one or more TMDC crystal heteroepitaxially grown on one or more group III-Nitride (III-N) crystal. The TMDC crystal may be grown on a III-N heteroepitaxial crystal that has been grown on crystalline silicon substrate. One or more of III-N devices and silicon devices employing separated regions of the heteroepitaxial substrate may be integrated with a TMDC device fabricated on with the TMDC crystal. In some embodiments, impurity-doped III-N source/drain regions provide a low resistance coupling between metallization and a TMDC-channeled transistor.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee, Ravi Pillarisetty
  • Patent number: 10658586
    Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: James S. Clarke, Ravi Pillarisetty, Uday Shah, Tejaswi K. Indukuri, Niloy Mukherjee, Elijah V. Karpov, Prashant Majhi
  • Publication number: 20200144362
    Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
    Type: Application
    Filed: December 9, 2019
    Publication date: May 7, 2020
    Applicant: INTEL CORPORATION
    Inventors: Anand S. MURTHY, Glenn A. GLASS, Tahir GHANI, Ravi PILLARISETTY, Niloy MUKHERJEE, Jack T. KAVALIEROS, Roza KOTLYAR, Willy RACHMADY, Mark Y. LIU