Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: The disclosed technology generally relates to forming a titanium nitride layer, and more particularly to forming by atomic layer deposition a titanium nitride layer on a seed layer. In one aspect, a semiconductor structure comprises a semiconductor substrate comprising a non-metallic surface. The semiconductor structure additionally comprises a seed layer comprising silicon (Si) and nitrogen (N) conformally coating the non-metallic surface and a TiN layer conformally coating the seed layer. Aspects are also directed to methods of forming the semiconductor structures.

Abstract: Techniques are described herein for executing queries on distinct portions of a database object that has been separate into chunks and distributed across the volatile memories of a plurality of nodes in a clustered database system. The techniques involve redistributing the in-memory database object portions on changes to the clustered database system. Each node may maintain a mapping indicating which nodes in the clustered database system store which chunks, and timestamps indicating when each mapping entry was created or updated. A query coordinator may use the timestamps to select a database server instance with local in memory access to data required by a portion of a query to process that portion of the query.

Abstract: The disclosed technology generally relates to semiconductor processing and more particularly to placing a substrate in a semiconductor manufacturing equipment for processing, and to apparatuses for placing the substrate in the semiconductor manufacturing equipment. In one aspect, a method of calibrating a process position of a semiconductor substrate in a process chamber comprises securing a calibration substrate on a susceptor in a processing chamber under an open chamber condition using a securing device, wherein securing comprises preventing the substrate from sliding laterally on the susceptor by more than a predefined tolerance from a centered position relative to a susceptor center. The method additionally comprises subjecting the calibration substrate under a process condition different from the open chamber condition. The method additionally comprises transferring the calibration substrate from the susceptor using a robot arm.

Abstract: The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Abstract: The disclosed technology generally relates to forming a thin film comprising titanium nitride (TiN), and more particularly to forming by a cyclical vapor deposition process the thin film comprising (TiN).

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to liquid precursor injection apparatus and methods for depositing thin films. A method of injecting a liquid precursor into a thin film deposition chamber comprises delivering a vaporized liquid precursor into the thin film deposition chamber by atomizing the liquid precursor into atomized precursor droplets using a liquid injection unit and vaporizing the atomized precursor droplets into the vaporized liquid precursor in a vaporization chamber.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to an encapsulation layer for a semiconductor device having a chalcogenide material, and methods of forming the same. In one aspect, a method of fabricating a semiconductor device comprises providing a substrate having an exposed surface comprising a chalcogenide material. The method additionally comprises forming a low-electronegativity (low-?) metal oxide layer on the chalcogenide material by cyclically exposing the substrate to a low-? metal precursor and an oxygen precursor comprising O2, wherein the low-? metal of the metal precursor has an electronegativity of 1.6 or lower.

Abstract: Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal and an electrolyte; wherein the electrolyte is coupled between the active metal and the source/drain region when the transistor is an n-type metal oxide semiconductor (NMOS) transistor, and the active metal is coupled between the electrolyte and the source/drain region when the transistor is a p-type metal oxide semiconductor (PMOS) transistor.

Abstract: Infrastructure attacks are identified by monitoring system level activities using software agents deployed on respective operating systems and constructing, based on the system level activities, an execution graph comprising a plurality of execution trails. A connection to a remote server executing on a first one of the operating systems is identified, where the connection is initiated by a remote execution function executing on a second one of the operating systems. A connection is formed between the first operating system and the second operating system in a global execution trail in the execution graph. A new process created on the first operating system is determined to be associated with a logon session resulting from the connection, and behavior exhibited from the logon session is attributed to the global execution trail in the execution graph.

Abstract: Infrastructure attacks based on graph edge context are identified by receiving an execution graph constructed by a central service based on behaviors monitored by a plurality of agents deployed on respective systems including a first system. The execution graph comprises a plurality of execution trails. One or more tags are applied to each edge of an execution trail of the execution graph based on at least one of temporal context or spatial context associated with the edge. One or more behaviors associated with the edge of the execution trail happen across an enterprise infrastructure involving the first system. The execution trail enriched with the one or more tags is analyzed. An action that is performed to mitigate security risks in the execution graph is determined based on the analysis.

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Abstract: The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to liquid precursor injection apparatus and methods for depositing thin films. A method of injecting a liquid precursor into a thin film deposition chamber comprises delivering a vaporized liquid precursor into the thin film deposition chamber by atomizing the liquid precursor into atomized precursor droplets using a liquid injection unit and vaporizing the atomized precursor droplets into the vaporized liquid precursor in a vaporization chamber.

Abstract: The disclosed technology generally relates to semiconductor processing and more particularly to placing a substrate in a semiconductor manufacturing equipment for processing, and to apparatuses for placing the substrate in the semiconductor manufacturing equipment. In one aspect, a method of calibrating a process position of a semiconductor substrate in a process chamber comprises securing a calibration substrate on a susceptor in a processing chamber under an open chamber condition using a securing device, wherein securing comprises preventing the substrate from sliding laterally on the susceptor by more than a predefined tolerance from a centered position relative to a susceptor center. The method additionally comprises subjecting the calibration substrate under a process condition different from the open chamber condition. The method additionally comprises transferring the calibration substrate from the susceptor using a robot arm.

Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.