Abstract: Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.

Abstract: Systems and methods for reducing RRAM relaxation in crossbar array circuits for low current applications are provided. In some implementations, an apparatus comprises: a first row wire; a first column wire; an RRAM device; an access control device, wherein the RRAM device and the access control device serially connected and connecting between the first row wire and the first column wire, and wherein the RRAM device comprises: a first electrode; a first switching layer formed on the first electrode; and a second electrode formed on the first switching layer, wherein the first switching layer is doped with a first oxide material comprising SiO2, or Al2O3. The first electrode and the second electrode are, in some implementations, made of one of the following materials: Pt, Pd, Ta, Ti, Hf, W, TiN, and TaN.

Abstract: Provided are 3D One-Transistor-N-RRAM (1TNR) structures and One-Selector-One-RRAM (1S1R) structures and methods for manufacturing the same. An example 3D 1TNR structure comprises: a plurality of gate lines; and a plurality of crossbar arrays (e.g., a first crossbar array and a second crossbar array). The first and second crossbar arrays are positioned on a first vertical plane and a second vertical plane, respectively. Each crossbar array in the plurality of crossbar arrays includes a first plurality of bit lines and a second plurality of word lines; Each word line in the second plurality of word lines is connected to a source and a destination of a second transistor; and each gate line in the plurality of gate lines is connected to a gate of a first transistor located in the first crossbar array and a gate of a second transistor located in the second crossbar array.

Abstract: Technologies relating to increasing the surface area of selectors in crossbar array circuits are provided. An example apparatus includes: a substrate; a first line electrode formed on the substrate; an RRAM stack formed on the first line electrode, wherein the RRAM stack; an isolation layer formed beside the RRAM stack, wherein the isolation layer includes an upper surface and a sidewall, and a height from the upper surface to the first line electrode is 100 nanometers to 10 micrometers; a selector stack formed on the RRAM stack, the sidewall, and the upper surface; and a second line electrode formed on the selector stack.

Abstract: A micro light-emitting diode (LED) display assembly includes a backplane, a passivation layer on the backplane, a micro LED on the passivation layer, and a non-transparent metal housing on the passivation layer. The housing includes a base portion on the passivation layer, a sidewall portion upwardly extending from the base portion, a cap portion connected at a top of the sidewall portion, an orifice in the cap portion, and a notch in the cap portion and adjacent to the orifice. The assembly also includes a translucent filter positioned in the notch and covering the orifice, and a pocket defined by an enclosed area in between the sidewall portion, the cap portion, the filter, and the passivation layer. The micro LED is encased within the pocket such that light transmitted from the micro LED directly hits and passes through the filter.

Abstract: Technologies relating to folded crossbar array circuits and methods for reducing pitch match issues within folded crossbar array circuits and increasing the scalability of folded crossbar array circuits are disclosed. An example crossbar array circuit includes: a first folded column circuit folded as at least two portions; a first ADC; a first plurality of DACs; and a first plurality of access controls, wherein the first folded column circuit connected to the first ADC, the first plurality of DACs, and the first plurality of access controls. In some implementations, the three portions comprises a first column of crossbar devices, a second column of crossbar devices, and a third column of crossbar devices, and wherein the first column of crossbar devices, the second column of crossbar devices, and the third column of crossbar devices are configured to be controlled by the first plurality of access controls.

Abstract: The technology of a crossbar array circuit and method of improving thermal shielding are disclosed. An example apparatus includes a bottom wire; a first vertical thermal shielding layer formed on the bottom wire, a bottom electrode formed on the first vertical thermal shielding layer; a filament forming layer formed on the bottom electrode; a top electrode formed on the filament forming layer; a second vertical thermal shielding layer formed on the top electrode; a top wire formed on the second vertical thermal shielding layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the first vertical thermal shielding layer and the second vertical thermal shielding layer includes ReOx, RuOx, IrOx, ITO, a combination thereof, or an alloy or doping thereof (with or without other thermally conductive materials).

Abstract: Systems and methods for mitigating defects in a crossbar-based computing environment are disclosed. In some implementations, an apparatus comprises: a first row wire; a second row wire having a defective device; and a crossbar array configured to receive a first input signal. The defective device is associated with a defect pattern; the first row wire and the second row wire are located within the crossbar array; and the first input signal is configured to be provided to the first row wire. The apparatus further comprises a shuffling module connected to the crossbar array and configured to divert the input signal from the first row wire to the second row wire in accordance with a determination that the defect pattern is within a predefined approximation to a target circuit pattern associated with the first input signal.

Abstract: An example method includes: forming a bottom electrode on a substrate and forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide using a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status and the solid status of the bottom electrode oxide using a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and a top electrode on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive to a switching voltage being applied to the filament forming layer.

Abstract: Technologies relating to RRAM-based crossbar array circuits and more specifically to reducing row switch resistance error of in crossbar array circuits are disclosed. An example apparatus includes: a first Op-amp including a first inverting Op-amp input, a first non-inverting Op-amp input, and a first Op-amp output; a row switch device including a row switch input and a row switch output; a crossbar array including a row wire, a column wire, and a cross-point device connected between the row wire and the column wire. The row switch input is connected to the first Op-amp output; the row switch output is connected to the first inverting Op-amp input; and the row switch output is connected to the row wire.

Abstract: An RFID security device for product packaging is disclosed. The security device includes an RFID tag disposed on a first portion of a product package, and a booster antenna disposed on a second portion of the product package. The RFID tag and booster antenna are positioned on the product package so that the RFID tag will be electromagnetically coupled to the booster antenna when the product package is closed, and the RFID tag will be decoupled from the booster antenna when the product package is open.

Abstract: In some examples, a data representation is received that includes voxels relating to a volumetric property and a functional property of portions of a three-dimensional (3D) object to be formed by a 3D printing system, and trajectory voxels containing information to guide operation of a machine that manipulates portions of the 3D object during 3D printing. Information of the voxels relating to the volumetric property and the functional property and the information of the trajectory voxels are combined to produce instructions that control the 3D printing system to build the 3D object.

Abstract: A sensing structure in an example may include at least three electrodes along an interior surface of a reservoir from a top portion of the reservoir to a bottom portion of the reservoir wherein at least one of the electrodes is closer to at least another electrode at the top portion of the reservoir than at the bottom portion of the reservoir.

Abstract: A dual-purpose calibration system for an optical pressure sensitive paint considering static and sinusoidal pressure changes, and a calibration method, in which a dual-purpose calibration tube is used in common, are provided. In the dual-purpose calibration system, a dynamic adapter and a static adapter are replaced with each other to achieve switching between dynamic calibration and static calibration, so that two calibration methods, one static and the other dynamic, can be implemented by the dual-purpose calibration system. The switching between the dynamic calibration and the static calibration includes changing between the dynamic adapter and static adapter, and setting a sound source corresponding to the dynamic adapter or setting a gas source corresponding to the static adapter.

Abstract: Systems and methods for reducing RRAM relaxation in crossbar array circuits for low current applications are provided. In some implementations, an apparatus comprises: a first row wire; a first column wire; an RRAM device; an access control device, wherein the RRAM device and the access control device serially connected and connecting between the first row wire and the first column wire, and wherein the RRAM device comprises: a first electrode; a first switching layer formed on the first electrode; and a second electrode formed on the first switching layer, wherein the first switching layer is doped with a first oxide material comprising SiO2, or Al2O3. The first electrode and the second electrode are, in some implementations, made of one of the following materials: Pt, Pd, Ta, Ti, Hf, W, TiN, and TaN.

Abstract: Technologies relating to implementing memristor crossbar arrays using non-filamentary RRAM cells are disclosed. In some implementations, an apparatus comprises: a first row wire; a first column wire; a non-filamentary RRAM; and an access control device. The non-filamentary RRAM and the access control device are serially connected; the non-filamentary RRAM and the access control device connect the first row wire with the first column wire. The non-filamentary RRAM and the access control device may form a cross-point device. The cross-point device may be less than 40×40 nm2. A set current of the non-filamentary RRAM may be no more than 10 ?A; and a reset current of the non-filamentary RRAM is no more than 10 ?A. The access control device may comprise a transistor or a selector.

Abstract: The technology of a crossbar array circuit and method of improving thermal shielding are disclosed. An example apparatus includes a bottom wire; a first vertical thermal shielding layer formed on the bottom wire, a bottom electrode formed on the first vertical thermal shielding layer; a filament forming layer formed on the bottom electrode; a top electrode formed on the filament forming layer; a second vertical thermal shielding layer formed on the top electrode; a top wire formed on the second vertical thermal shielding layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer, and wherein a material of the first vertical thermal shielding layer and the second vertical thermal shielding layer includes ReOx, RuOx, IrOx, ITO, a combination thereof, or an alloy or doping thereof (with or without other thermally conductive materials).

Abstract: Technologies relating to folded crossbar array circuits and methods for reducing pitch match issues within folded crossbar array circuits and increasing the scalability of folded crossbar array circuits are disclosed. An example crossbar array circuit includes: a first folded column circuit folded as at least two portions; a first ADC; a first plurality of DACs; and a first plurality of access controls, wherein the first folded column circuit connected to the first ADC, the first plurality of DACs, and the first plurality of access controls. In some implementations, the three portions comprises a first column of crossbar devices, a second column of crossbar devices, and a third column of crossbar devices, and wherein the first column of crossbar devices, the second column of crossbar devices, and the third column of crossbar devices are configured to be controlled by the first plurality of access controls.

Abstract: Technologies relating to improving LRS data retention and reliability in RRAM-based crossbar array circuits are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive a switching voltage being applied to the filament forming layer. The filament forming layer may be made of one of the following materials: HfOxSiy, HfOxNy, HfOxAly, HfOx doped with SiO2, HfOx doped with Al2O3, HfOx doped with N, HfOx doped with Si3N4, HfOx doped with AlN, or a combination thereof. The bottom electrode or the top electrode may be made of one of the following materials: Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, Ru, TaN, NbN, a combination therefore, or an alloy with other electrically conductive materials.

Abstract: In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor.