Patents by Inventor Ning Shi
Ning Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190304965Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Publication number: 20190259413Abstract: The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a trailing shield, a main pole, a MAMR stack disposed between the trailing shield and the main pole, side shields surrounding at least a portion of the main pole, and a structure disposed between the side shields and the main pole at a media facing surface (WS). The structure is fabricated from a material that is thermally conductive and electrically insulating/dissipative. The material has a thermal conductivity of at least 50 W/(m*K) and an electrical resistivity of at least 105 ?*m. The structure helps dissipate joule heating generated from either the main pole or the MAMR stack into surrounding area without electrical shunting, leading to reduced heating or break-down induced failures.Type: ApplicationFiled: February 14, 2019Publication date: August 22, 2019Applicant: Western Digital Technologies, Inc.Inventors: Quang LE, Hongquan JIANG, Ning SHI, Alexander M. ZELTSER
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Patent number: 10373947Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.Type: GrantFiled: July 25, 2018Date of Patent: August 6, 2019Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Publication number: 20190074274Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.Type: ApplicationFiled: November 1, 2018Publication date: March 7, 2019Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Patent number: 10157904Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.Type: GrantFiled: March 31, 2017Date of Patent: December 18, 2018Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Publication number: 20180342499Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.Type: ApplicationFiled: July 25, 2018Publication date: November 29, 2018Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Publication number: 20180286852Abstract: A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Patent number: 10067999Abstract: Database replication is performed by tracking sequence numbers associated with binary change logs. At a producer cluster, a binary change log is generated based on a write transaction made to a database partition in the producer cluster. Included with the binary change log is a sequence number corresponding to the write transaction. The binary change log is transmitted from the producer cluster to a consumer cluster, where a determination is made whether to apply the binary change log based on the included sequence number. The binary change log is then applied to a database partition in the consumer cluster. The sequence number is stored at the consumer cluster by combining the sequence number with a numerical range having a first number and a second number, where the second number has a value corresponding to the most recent binary change log applied to the database partition in the consumer cluster.Type: GrantFiled: September 14, 2017Date of Patent: September 4, 2018Assignee: VoltDB, Inc.Inventors: Ning Shi, Walter Weiss, Yang Lu, Rui Shen, Manju James
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Patent number: 10062682Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.Type: GrantFiled: May 25, 2017Date of Patent: August 28, 2018Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Shekar Mallikarjunaswamy, Ning Shi
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Patent number: 9947358Abstract: An apparatus comprises a slider having a trailing edge and a leading edge. A laser diode unit comprises a submount and a laser diode mounted to the submount. The submount includes a mounting surface affixed to a first surface of the slider at the trailing edge such that a first surface of the submount faces toward the leading edge of the slider. A thermally conductive material covers the first surface of the submount and at least a portion of the first surface of the slider. The thermally conductive material serves as a thermal conduction pathway between the submount and the slider.Type: GrantFiled: August 16, 2017Date of Patent: April 17, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: Yuhang Cheng, Scott Franzen, Zoran Jandric, James Gary Wessel, Ning Shi
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Publication number: 20180101589Abstract: Database replication is performed by tracking sequence numbers associated with binary change logs. At a producer cluster, a binary change log is generated based on a write transaction made to a database partition in the producer cluster. Included with the binary change log is a sequence number corresponding to the write transaction. The binary change log is transmitted from the producer cluster to a consumer cluster, where a determination is made whether to apply the binary change log based on the included sequence number. The binary change log is then applied to a database partition in the consumer cluster. The sequence number is stored at the consumer cluster by combining the sequence number with a numerical range having a first number and a second number, where the second number has a value corresponding to the most recent binary change log applied to the database partition in the consumer cluster.Type: ApplicationFiled: September 14, 2017Publication date: April 12, 2018Inventors: Ning Shi, Walter Weiss, Yang Lu, Rui Shen, Manju James
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Patent number: 9911728Abstract: A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.Type: GrantFiled: February 28, 2017Date of Patent: March 6, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Ning Shi, Lingpeng Guan, Madhur Bobde
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Patent number: 9805747Abstract: Ionized physical vapor deposition (IPVD) is used to form a magnetic recording disk drive write head main pole with thin side gap layers and a thicker leading gap layer. A metal or metal alloy is formed by IPVD in a trench with a bottom and outwardly sloping sidewalls. An optional Ru seed layer is deposited on the metal or metal alloy. This is followed by atomic layer deposition (ALD) of a Ru smoothing layer. If the IPVD results in metal or metal alloy side gap layers with a rough surface, the ALD process is modified, resulting in a smooth Ru smoothing layer that does not replicate the rough surface of the side gap layers.Type: GrantFiled: August 17, 2015Date of Patent: October 31, 2017Assignee: Western Digital Technologies, Inc.Inventors: April D. Hixson-Goldsmith, Ning Shi, Kyusik Shin, Suping Song, Brian R. York
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Patent number: 9754617Abstract: An apparatus comprises a slider having a trailing edge and a leading edge. A laser diode unit comprises a submount and a laser diode mounted to the submount. The submount includes a mounting surface affixed to a first surface of the slider at the trailing edge such that a first surface of the submount faces toward the leading edge of the slider. A thermally conductive material covers the first surface of the submount and at least a portion of the first surface of the slider. The thermally conductive material serves as a thermal conduction pathway between the submount and the slider.Type: GrantFiled: February 23, 2015Date of Patent: September 5, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Yuhang Cheng, Scott Franzen, Zoran Jandric, James Gary Wessel, Ning Shi
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Publication number: 20170179107Abstract: A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.Type: ApplicationFiled: February 28, 2017Publication date: June 22, 2017Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Ning Shi, Lingpeng Guan, Madhur Bobde
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Patent number: 9639571Abstract: A distributed shared-nothing database provides serializable isolation for transactions and includes a mechanism for adding storage and processing capacity to the database without stopping the database from processing transactions.Type: GrantFiled: November 20, 2014Date of Patent: May 2, 2017Assignee: VOLTDB, INC.Inventors: Ariel D. Weisberg, Ning Shi, Steven Z. Cooper, Stefano M. Santoro
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Patent number: 9583586Abstract: A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.Type: GrantFiled: December 22, 2015Date of Patent: February 28, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Ning Shi, Lingpeng Guan, Madhur Bobde
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Publication number: 20170053668Abstract: Ionized physical vapor deposition (IPVD) is used to form a magnetic recording disk drive write head main pole with thin side gap layers and a thicker leading gap layer. A metal or metal alloy is formed by IPVD in a trench with a bottom and outwardly sloping sidewalls. An optional Ru seed layer is deposited on the metal or metal alloy. This is followed by atomic layer deposition (ALD) of a Ru smoothing layer. If the IPVD results in metal or metal alloy side gap layers with a rough surface, the ALD process is modified, resulting in a smooth Ru smoothing layer that does not replicate the rough surface of the side gap layers.Type: ApplicationFiled: August 17, 2015Publication date: February 23, 2017Inventors: April D. Hixson-Goldsmith, Ning Shi, Kyusik Shin, Suping Song, Brian R. York
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Patent number: 9558775Abstract: An apparatus comprises a slider of a magnetic recording head, a submount, and an interface defined between the slider and the submount. A laser diode is connected to the submount. A metal layer is provided at the interface between the slider and the submount. The metal layer connects at least about 30% of the surface area of the submount at the interface to the slider and serves as a thermal conduction pathway between the submount and the slider.Type: GrantFiled: February 19, 2015Date of Patent: January 31, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Zoran Jandric, Ning Shi, James Gary Wessel, Lars Ahlen, Neil Zuckerman, Tyler Perry
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Patent number: 9548069Abstract: The present invention generally relates to a method for forming a smooth gap of a damascene write pole. An opening having a side wall with a first angle with respect to vertical is formed in a fill layer, and a first non-magnetic layer is deposited into the opening by ion beam deposition. The ion beam is delivered to the side wall at a second angle with respect to vertical. The ratio of the first angle to the second angle ranges from about 250 to about 3.5.Type: GrantFiled: March 14, 2013Date of Patent: January 17, 2017Assignee: HGST NETHERLANDS B.V.Inventors: Ning Shi, Xiaoyu Xu, Sue S. Zhang