Abstract: A technique monitors input/output (I/O) and Persistent Reservation (PR) activity patterns to detect degraded performance of a highly available and fault tolerant application executing in a multi-site disaster recovery (DR) environment. Multiple instances of the application execute in different virtual machines (VMs) of a compute layer within a guest clustering configuration that extends across clusters of the sites. A storage layer of the clusters provides shared storage to the multiple VMs across the multiple sites. One of the sites is configured as an active storage site configured to receive and service I/O requests from the compute layer. A single instance of the application is active at a time and configured as a “compute owner” of the shared storage to issue the I/O requests to the shared storage. The compute owner and active storage site may not be co-located on the same site, leading to excessive I/O and PR activity patterns indicative of degraded performance.

Abstract: Methods and server systems for computing fraud risk scores for various merchants associated with an acquirer described herein. The method performed by a server system includes accessing merchant-related transaction data including merchant-related transaction indicators associated with a merchant from a transaction database. Method includes generating a merchant-related transaction features based on the merchant-related indicators. Method includes generating via risk prediction models, for a payment transaction with the merchant, merchant health and compliance risk scores, merchant terminal risk scores, merchant chargeback risk scores, and merchant activity risk scores based on the merchant-related transaction features. Method includes facilitating transmission of a notification message to an acquirer server associated with the merchant.

Abstract: In implementations of systems for predicting a terminal event, a computing device implements a termination system to receive input data defining a period of time and a maximum event threshold. This system uses a classification model to generate event scores for a plurality of entity devices. Each of the event scores indicates a probability of an event occurrence for a corresponding entity device within a period of time. The plurality of entity devices are segmented into a first segment and a second segment based on an event score threshold. Entity devices included in the first segment have event scores greater than the event score threshold and entity devices included in the second segment have event scores below the event score threshold. The termination system generates an indication of a probability that a number of event occurrences for the entity devices included in the second segment exceeds the maximum even threshold within the period of time.

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Abstract: Methods and apparatus for instruction elimination through hardware driven memoization of loop instances. A hardware-based loop memoization technique learns repeating sequences of loops and transparently removes instructions for the loop instructions from instruction sequences while making their output available to dependent instructions as if the loop instructions had been executed. A path-based predictor is implemented at the front-end to predict these loop instances and remove their instructions from instruction sequences. A novel memoization prediction micro-operation (Uop) is inserted into the instruction sequence for instances of loops that are predicted to be memoized. The memoization prediction Uop is used to compare the input signature (expected set of input values for the loop) with the actual signature to determine correct and incorrect predictions.

Abstract: A method of image processing and classifying target entities with an image is disclosed that may include applying a contrast amplification procedure to a Lightness parameter associated with an input image, to amplify contrast of the input image and obtain an amplified-contrast image. The method may further include de-noising the amplified-contrast image by iteratively performing on the amplified-contrast image a blur correction, an erosion correction, and a dilation correction, to obtain a de-noised image corresponding to the amplified-contrast image. The method may further include determining edges of each of one or more target entities associated with the input image from the de-noised image and identifying the one or more target entities associated with the input image based on the identified edges, to generate a contoured image. The method may further include classifying the one or more target entities into one or more predefined classes, using a classification model.

Abstract: Methods, systems, and computer programs are presented for enabling any sandboxed user-defined function code to securely access the Internet via a cloud data platform. A remote procedure call is received by a cloud data platform from a user-defined function (UDF) executing within a sandbox process. The UDF includes code related to at least one operation to be performed. The cloud data platform provides an overlay network to establish a secure egress path for UDF external access. The cloud data platform enables the UDF executing in the sandbox process to initiate a network call.

Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating front-end branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to throttling a code fetch for speculative code paths are described. In an embodiment, a first storage structure stores a reference to a code line in response to a request to be received from a cache. A second storage structure to store a reference to the code line in response to an update to an Instruction Dispatch Queue (IDQ). Logic circuitry controls additional code line fetch operations based at least in part on a comparison of a number of ongoing speculative code fetches and a determination that the code line is speculative. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of the present disclosure generally relate to a processing system for forming one or more layers of a photodiode. In one embodiment, the processing system includes a transfer chamber, a plurality of processing chambers, and a controller configured to cause a process to be performed in the processing system. The process includes performing a pre-clean process on a substrate, aligning and placing a first mask on the substrate, depositing a first layer on the substrate, and depositing a second layer on the substrate. The processing system can form layers of a photodiode in a low defect, cost effective, and high utilization manner.

Abstract: Apparatus and method for memoizing repeat function calls are described herein. An apparatus embodiment includes: uop buffer circuitry to identify a function for memoization based on retiring micro-operations (uops) from a processing pipeline; memoization retirement circuitry to generate a signature of the function which includes input and output data of the function; a memoization data structure to store the signature; and predictor circuitry to detect an instance of the function to be executed by the processing pipeline and to responsively exclude a first subset of uops associated with the instance from execution when a confidence level associated with the function is above a threshold. One or more instructions that are data-dependent on execution of the instance is then provided with the output data of the function from the memoization data structure.

Abstract: In one embodiment, a processor includes a branch predictor to predict whether a branch instruction is to be taken and a branch target buffer (BTB) coupled to the branch predictor. The branch target buffer may be segmented into a first cache portion and a second cache portion, where, in response to an indication that the branch is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: a decode circuit to decode a branch instruction, the branch instruction comprising a hint field to provide spatial information regarding a distance between the branch instruction and a target instruction of the branch instruction; a branch predictor to predict whether the branch instruction is to be taken; and a branch target buffer (BTB) coupled to the branch predictor. The BTB, based at least in part on the spatial information, may allocate an entry for the branch instruction in one of a first portion of the BTB and a second portion of the BTB. Other embodiments are described and claimed.

Abstract: A system for automatically constructing a flight plan that aligns with a boundary line is provided. The system has a controller that is configured to: automatically select a set of geographical (geo) coordinate waypoints along a boundary line using waypoints from the geographical database responsive to flight crew input; refine the set of geo coordinate waypoints using a calculated turn initiation distance and a turn completion distance for every waypoint; further refine the refined set of geo coordinate waypoints based on the course change between waypoints; generate a set of courses and distances between waypoints through computing, for each set of two consecutive waypoints in the further refined set of geo coordinate waypoints, the course and distance between the two consecutive waypoints; and construct the flight plan based on the waypoints in the further refined set of geo coordinate waypoints and the set of courses and distances between waypoints.

Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating frontend branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to Instruction Set Architecture (ISA) and/or microarchitecture for early pipeline re-steering using load address prediction to mitigate branch misprediction penalties are described. In an embodiment, decode circuitry decodes a load instruction and Load Address Predictor (LAP) circuitry issues a load prefetch request to memory for data for a load operation of the load instruction. Compute circuitry executes an outcome for a branch operation of the load instruction based on the data from the load prefetch request. And re-steering circuitry transmits a signal to cause flushing of data associated with the load instruction in response to a mismatch between the outcome for the branch operation and a stored prediction value for the branch. Other embodiments are also disclosed and claimed.

Abstract: A system for automatically constructing a flight plan that aligns with a boundary line is provided. The system has a controller that is configured to: automatically select a set of geographical (geo) coordinate waypoints along a boundary line using waypoints from the geographical database responsive to flight crew input; refine the set of geo coordinate waypoints using a calculated turn initiation distance and a turn completion distance for every waypoint; further refine the refined set of geo coordinate waypoints based on the course change between waypoints; generate a set of courses and distances between waypoints through computing, for each set of two consecutive waypoints in the further refined set of geo coordinate waypoints, the course and distance between the two consecutive waypoints; and construct the flight plan based on the waypoints in the further refined set of geo coordinate waypoints and the set of courses and distances between waypoints.

Abstract: Substrate carrier apparatus having a hard mask are disclosed herein. In some embodiments, a substrate carrier apparatus includes a carrier body having a support surface to support a substrate; and a mask assembly disposed above the support surface. The mask assembly includes an annular frame disposed atop the support surface; and a hard mask coupled to and disposed within the annular frame above the support surface, wherein the hard mask includes one or more openings arranged in a predetermined pattern and disposed through the hard mask, and wherein the hard mask includes a plurality of spacer elements extending from a bottom surface of the hard mask.

Abstract: An electrostatic chucking force tool is described that may be used on workpiece carriers for micromechanical and semiconductor processing. One example includes a workpiece fitting to hold a workpiece when gripped by an electrostatic chucking force by an electrostatic chuck, an arm coupled to the workpiece fitting to pull the workpiece through the workpiece fitting laterally across the chuck, and a force gauge coupled to the arm to measure an amount of force with which the workpiece fitting is pulled by the arm in order to move the workpiece.