Patents by Inventor Niranjan Kumar
Niranjan Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250117299Abstract: A technique monitors input/output (I/O) and storage ownership takeover activity patterns to detect degraded performance of a highly available and fault tolerant application executing in a multi-site environment. Multiple instances of the application execute in different containers or pods running on virtual machines (VMs) of a compute layer within a containerized (e.g., Kubernetes) clustering configuration that extends across clusters of the sites. A storage layer of the clusters provides shared storage to the pods running on the VMs across the multiple sites. One of the sites is configured as an active storage site configured to receive and service I/O requests from the compute layer. A single instance of the application is active at a time and configured as a “compute owner” of the shared storage to issue the I/O requests to the shared storage.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Inventors: Anish Jain, Prakash Narayanasamy, Praveen Kumar Padia, Vivek Venkatesan, Niranjan Sanjiv Pendharkar, Shubham Sharma
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Patent number: 12244558Abstract: This disclosure provides methods and techniques of performing source network address translation (SNAT) at a packet sender (e.g., a client device) instead of a gateway device (e.g., a proxy device). The present disclosure performs a SNAT operation at the packet sender, relieving the gateway device from the SNAT operation to perform other duties (e.g., policy enforcement). An example method of network address translation includes modifying, by a processing device at a data packet origination device (e.g., a client device), network address information in an internet protocol (IP) header of a packet using a public IP address. The method further includes sending the packet to a public network based on the public IP address.Type: GrantFiled: September 29, 2023Date of Patent: March 4, 2025Assignee: Snowflake Inc.Inventors: Brandon S. Baker, Niranjan Kumar Sharma, Xuguang Yang, Haowei Yu
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Patent number: 12208732Abstract: Systems and methods for a self-adjusting vehicle mirror. The mirror automatically locates the face of the driver or another passenger, and orients the mirror to provide the driver/passenger face with a desired view from the mirror. The mirror may continue to reorient itself as the driver or passenger shifts position, to continuously provide a desired field of view even as he or she changes position over time. In certain embodiments, the mirror system of the disclosure can be a self-contained system, with the mirror, mirror actuator, camera, and computing device all contained within the mirror housing as a single integrated unit.Type: GrantFiled: January 27, 2020Date of Patent: January 28, 2025Assignee: NVIDIA CorporationInventors: Feng Hu, Niranjan Avadhanam, Ratin Kumar, Simon John Baker
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Patent number: 12211308Abstract: Interactions with virtual systems may be difficult when users inadvertently fail to provide sufficient information to proceed with their requests. Certain types of inputs, such as auditory inputs, may lack sufficient information to properly provide a response to the user. Additional information, such as image data, may enable user gestures or poses to supplement the auditory inputs to enable response generation without requesting additional information from users.Type: GrantFiled: August 31, 2021Date of Patent: January 28, 2025Assignee: Nvidia CorporationInventors: Sakthivel Sivaraman, Nishant Puri, Yuzhuo Ren, Atousa Torabi, Shubhadeep Das, Niranjan Avadhanam, Sumit Kumar Bhattacharya, Jason Roche
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Publication number: 20250027150Abstract: The present disclosure provides compositions, methods, systems, and devices for polynucleotide processing and analyte characterization. Such polynucleotide processing may be useful for a variety of applications, including analyte characterization by polynucleotide sequencing. The compositions, methods, systems, and devices disclosed herein generally describe barcoded oligonucleotides, which can be bound to a bead, such as a gel bead, useful for characterizing one or more analytes including, for example, protein (e.g., cell surface or intracellular proteins), genomic DNA, and RNA (e.g., mRNA or CRISPR guide RNAs). Also described herein, are barcoded labelling agents and oligonucleotide molecules useful for “tagging” analytes for characterization.Type: ApplicationFiled: July 26, 2024Publication date: January 23, 2025Inventors: Phillip Belgrader, Zachary Bent, Rajiv Bharadwaj, Vijay Kumar Sreenivasa Gopalan, Josephine Harada, Christopher Hindson, Mohammad Rahimi Lenji, Michael Ybarra Lucero, Geoffrey McDermott, Elliott Meer, Tarjei Sigurd Mikkelsen, Christopher Joachim O'Keeffe, Katherine Pfeiffer, Andrew D. Price, Paul Ryvkin, Serge Saxonov, John R. Stuelpnagel, Jessica Michele Terry, Tobias Daniel Wheeler, Indira Wu, Solongo Batjargal Ziraldo, Stephane Claude Boutet, Sarah Taylor, Niranjan Srinivas
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Patent number: 12190114Abstract: In one embodiment, a processor includes a branch predictor to predict whether a branch instruction is to be taken and a branch target buffer (BTB) coupled to the branch predictor. The branch target buffer may be segmented into a first cache portion and a second cache portion, where, in response to an indication that the branch is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction. Other embodiments are described and claimed.Type: GrantFiled: December 22, 2020Date of Patent: January 7, 2025Assignee: Intel CorporationInventors: Niranjan Kumar Soundararajan, Sreenivas Subramoney, Sr Swamy Saranam Chongala
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Publication number: 20240364744Abstract: Systems and methods are disclosed for securely executing user-defined functions within a cloud data platform. A method involves receiving, via hardware processors, a request to execute a user-defined function (UDF) contained within a sandbox process. The UDF comprises code for performing specified operations that necessitate access to external resources. To facilitate this access, a secure egress path is established using an overlay network designed to isolate the UDF's network traffic from other processes. Authentication and authorization details for the UDF are managed externally to the sandbox process, ensuring that the UDF's functionality remains orthogonal to the cloud data platform's operations. This approach enables the secure and controlled execution of UDFs, allowing them to interact with external systems while maintaining the integrity and security of the cloud data platform environment.Type: ApplicationFiled: January 31, 2024Publication date: October 31, 2024Inventors: Brandon S. Baker, Derek Denny-Brown, Michael A. Halcrow, Sven Tenzing Choden Konigsmark, Niranjan Kumar Sharma, Nitya Kumar Sharma, Haowei Yu, Andong Zhan
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SYSTEM AND METHOD TO REDUCE POWER CONSUMPTION BY USING ADAPTIVE TRANSMIT POWER DURING SNIFF ATTEMPTS
Publication number: 20240298260Abstract: Systems and methods for reducing power consumption by using adaptive transmit power during sniff intervals are disclosed. The central device transmits the first packet of the sniff interval using the previously negotiated transmit power. After the central device receives a response from the peripheral device, the central device uses a lower transmit power for subsequent POLL packets during that sniff interval. This scheme may reduce the power consumption of the central device significantly, especially when a large number of packets are transmitted during each sniff interval.Type: ApplicationFiled: March 2, 2023Publication date: September 5, 2024Inventors: Karthik Gunturi, Sunit Pujari, Niranjan Kumar Jonnada, Venkat Rao Gunturu -
Patent number: 12020033Abstract: Apparatus and method for memorizing repeat function calls are described herein. An apparatus embodiment includes: uop buffer circuitry to identify a function for memorization based on retiring micro-operations (uops) from a processing pipeline; memorization retirement circuitry to generate a signature of the function which includes input and output data of the function; a memorization data structure to store the signature; and predictor circuitry to detect an instance of the function to be executed by the processing pipeline and to responsively exclude a first subset of uops associated with the instance from execution when a confidence level associated with the function is above a threshold. One or more instructions that are data-dependent on execution of the instance is then provided with the output data of the function from the memorization data structure.Type: GrantFiled: December 24, 2020Date of Patent: June 25, 2024Assignee: Intel CorporationInventors: Niranjan Kumar Soundararajan, Sreenivas Subramoney, Jayesh Gaur, S R Swamy Saranam Chongala
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Publication number: 20240103874Abstract: Methods and apparatus for instruction elimination through hardware driven memoization of loop instances. A hardware-based loop memoization technique learns repeating sequences of loops and transparently removes instructions for the loop instructions from instruction sequences while making their output available to dependent instructions as if the loop instructions had been executed. A path-based predictor is implemented at the front-end to predict these loop instances and remove their instructions from instruction sequences. A novel memoization prediction micro-operation (Uop) is inserted into the instruction sequence for instances of loops that are predicted to be memoized. The memoization prediction Uop is used to compare the input signature (expected set of input values for the loop) with the actual signature to determine correct and incorrect predictions.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Niranjan Kumar Soundararajan, Sreenivas Subramoney, Jayesh Gaur
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Publication number: 20240087288Abstract: A method of image processing and classifying target entities with an image is disclosed that may include applying a contrast amplification procedure to a Lightness parameter associated with an input image, to amplify contrast of the input image and obtain an amplified-contrast image. The method may further include de-noising the amplified-contrast image by iteratively performing on the amplified-contrast image a blur correction, an erosion correction, and a dilation correction, to obtain a de-noised image corresponding to the amplified-contrast image. The method may further include determining edges of each of one or more target entities associated with the input image from the de-noised image and identifying the one or more target entities associated with the input image based on the identified edges, to generate a contoured image. The method may further include classifying the one or more target entities into one or more predefined classes, using a classification model.Type: ApplicationFiled: May 9, 2023Publication date: March 14, 2024Inventors: TANIYA SAINI, NIRANJAN KUMAR MANJUNATH, ASHOK AJAD, ARBAAZ MOHAMMAD SHAIKH, NISARGA KRISHNEGOWDA
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Patent number: 11930045Abstract: Methods, systems, and computer programs are presented for enabling any sandboxed user-defined function code to securely access the Internet via a cloud data platform. A remote procedure call is received by a cloud data platform from a user-defined function (UDF) executing within a sandbox process. The UDF includes code related to at least one operation to be performed. The cloud data platform provides an overlay network to establish a secure egress path for UDF external access. The cloud data platform enables the UDF executing in the sandbox process to initiate a network call.Type: GrantFiled: April 28, 2023Date of Patent: March 12, 2024Assignee: Snowflake Inc.Inventors: Brandon S. Baker, Derek Denny-Brown, Michael A. Halcrow, Sven Tenzing Choden Konigsmark, Niranjan Kumar Sharma, Nitya Kumar Sharma, Haowei Yu, Andong Zhan
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Patent number: 11928472Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating front-end branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 26, 2020Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Gilles Pokam, Jared Warner Stark, IV, Niranjan Kumar Soundararajan, Oleg Ladin
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Publication number: 20230195464Abstract: Methods and apparatus relating to throttling a code fetch for speculative code paths are described. In an embodiment, a first storage structure stores a reference to a code line in response to a request to be received from a cache. A second storage structure to store a reference to the code line in response to an update to an Instruction Dispatch Queue (IDQ). Logic circuitry controls additional code line fetch operations based at least in part on a comparison of a number of ongoing speculative code fetches and a determination that the code line is speculative. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Anant Vithal Nori, Prathmesh Kallurkar, Sreenivas Subramoney, Niranjan Kumar Soundararajan
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Publication number: 20230185718Abstract: Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Anant Vithal Nori, Prathmesh Kallurkar, Niranjan Kumar Soundararajan, Sreenivas Subramoney, Lihu Rappoport, Hanna Alam, Adrian Moga, Ronak Singhal
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Patent number: 11414740Abstract: Embodiments of the present disclosure generally relate to a processing system for forming one or more layers of a photodiode. In one embodiment, the processing system includes a transfer chamber, a plurality of processing chambers, and a controller configured to cause a process to be performed in the processing system. The process includes performing a pre-clean process on a substrate, aligning and placing a first mask on the substrate, depositing a first layer on the substrate, and depositing a second layer on the substrate. The processing system can form layers of a photodiode in a low defect, cost effective, and high utilization manner.Type: GrantFiled: May 1, 2020Date of Patent: August 16, 2022Assignee: Applied Materials, Inc.Inventors: Alexander N. Lerner, Roey Shaviv, Michael P. Karazim, Kevin Vincent Moraes, Steven V. Sansoni, Andrew J. Constant, Jeffrey Allen Brodine, Kim Ramkumar Vellore, Amikam Sade, Niranjan Kumar
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Publication number: 20220206816Abstract: Apparatus and method for memoizing repeat function calls are described herein. An apparatus embodiment includes: uop buffer circuitry to identify a function for memoization based on retiring micro-operations (uops) from a processing pipeline; memoization retirement circuitry to generate a signature of the function which includes input and output data of the function; a memoization data structure to store the signature; and predictor circuitry to detect an instance of the function to be executed by the processing pipeline and to responsively exclude a first subset of uops associated with the instance from execution when a confidence level associated with the function is above a threshold. One or more instructions that are data-dependent on execution of the instance is then provided with the output data of the function from the memoization data structure.Type: ApplicationFiled: December 24, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Niranjan Kumar Soundararajan, Sreenivas Subramoney, Jayesh Gaur, S R Swamy Saranam Chongala
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Publication number: 20220197662Abstract: In one embodiment, a processor includes: a decode circuit to decode a branch instruction, the branch instruction comprising a hint field to provide spatial information regarding a distance between the branch instruction and a target instruction of the branch instruction; a branch predictor to predict whether the branch instruction is to be taken; and a branch target buffer (BTB) coupled to the branch predictor. The BTB, based at least in part on the spatial information, may allocate an entry for the branch instruction in one of a first portion of the BTB and a second portion of the BTB. Other embodiments are described and claimed.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventors: NIRANJAN KUMAR SOUNDARARAJAN, SREENIVAS SUBRAMONEY, SR SWAMY SARANAM CHONGALA
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Publication number: 20220197657Abstract: In one embodiment, a processor includes a branch predictor to predict whether a branch instruction is to be taken and a branch target buffer (BTB) coupled to the branch predictor. The branch target buffer may be segmented into a first cache portion and a second cache portion, where, in response to an indication that the branch is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction. Other embodiments are described and claimed.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventors: NIRANJAN KUMAR SOUNDARARAJAN, SREENIVAS SUBRAMONEY, SR SWAMY SARANAM CHONGALA
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Patent number: 11348472Abstract: A system for automatically constructing a flight plan that aligns with a boundary line is provided. The system has a controller that is configured to: automatically select a set of geographical (geo) coordinate waypoints along a boundary line using waypoints from the geographical database responsive to flight crew input; refine the set of geo coordinate waypoints using a calculated turn initiation distance and a turn completion distance for every waypoint; further refine the refined set of geo coordinate waypoints based on the course change between waypoints; generate a set of courses and distances between waypoints through computing, for each set of two consecutive waypoints in the further refined set of geo coordinate waypoints, the course and distance between the two consecutive waypoints; and construct the flight plan based on the waypoints in the further refined set of geo coordinate waypoints and the set of courses and distances between waypoints.Type: GrantFiled: June 17, 2020Date of Patent: May 31, 2022Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Sanju Kuriakose, Anoop S, Sabu Mathew, Niranjan Kumar, Jan Hart, Janaki Seetharaman