Patents by Inventor Niranjan Kumar

Niranjan Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11414740
    Abstract: Embodiments of the present disclosure generally relate to a processing system for forming one or more layers of a photodiode. In one embodiment, the processing system includes a transfer chamber, a plurality of processing chambers, and a controller configured to cause a process to be performed in the processing system. The process includes performing a pre-clean process on a substrate, aligning and placing a first mask on the substrate, depositing a first layer on the substrate, and depositing a second layer on the substrate. The processing system can form layers of a photodiode in a low defect, cost effective, and high utilization manner.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: August 16, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Alexander N. Lerner, Roey Shaviv, Michael P. Karazim, Kevin Vincent Moraes, Steven V. Sansoni, Andrew J. Constant, Jeffrey Allen Brodine, Kim Ramkumar Vellore, Amikam Sade, Niranjan Kumar
  • Patent number: 11348472
    Abstract: A system for automatically constructing a flight plan that aligns with a boundary line is provided. The system has a controller that is configured to: automatically select a set of geographical (geo) coordinate waypoints along a boundary line using waypoints from the geographical database responsive to flight crew input; refine the set of geo coordinate waypoints using a calculated turn initiation distance and a turn completion distance for every waypoint; further refine the refined set of geo coordinate waypoints based on the course change between waypoints; generate a set of courses and distances between waypoints through computing, for each set of two consecutive waypoints in the further refined set of geo coordinate waypoints, the course and distance between the two consecutive waypoints; and construct the flight plan based on the waypoints in the further refined set of geo coordinate waypoints and the set of courses and distances between waypoints.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 31, 2022
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Sanju Kuriakose, Anoop S, Sabu Mathew, Niranjan Kumar, Jan Hart, Janaki Seetharaman
  • Publication number: 20210343159
    Abstract: A system for automatically constructing a flight plan that aligns with a boundary line is provided. The system has a controller that is configured to: automatically select a set of geographical (geo) coordinate waypoints along a boundary line using waypoints from the geographical database responsive to flight crew input; refine the set of geo coordinate waypoints using a calculated turn initiation distance and a turn completion distance for every waypoint; further refine the refined set of geo coordinate waypoints based on the course change between waypoints; generate a set of courses and distances between waypoints through computing, for each set of two consecutive waypoints in the further refined set of geo coordinate waypoints, the course and distance between the two consecutive waypoints; and construct the flight plan based on the waypoints in the further refined set of geo coordinate waypoints and the set of courses and distances between waypoints.
    Type: Application
    Filed: June 17, 2020
    Publication date: November 4, 2021
    Applicant: Honeywell International Inc.
    Inventors: Sanju Kuriakose, Anoop S, Sabu Mathew, Niranjan Kumar, Jan Hart, Janaki Seetharaman
  • Patent number: 11047039
    Abstract: Substrate carrier apparatus having a hard mask are disclosed herein. In some embodiments, a substrate carrier apparatus includes a carrier body having a support surface to support a substrate; and a mask assembly disposed above the support surface. The mask assembly includes an annular frame disposed atop the support surface; and a hard mask coupled to and disposed within the annular frame above the support surface, wherein the hard mask includes one or more openings arranged in a predetermined pattern and disposed through the hard mask, and wherein the hard mask includes a plurality of spacer elements extending from a bottom surface of the hard mask.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: June 29, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Alexander Lerner, Kim Vellore, Ami Sade, Steven Sansoni, Andrew Constant, Kevin Moraes, Roey Shaviv, Niranjan Kumar, Jeffrey Brodine, Michael Karazim
  • Patent number: 10879094
    Abstract: An electrostatic chucking force tool is described that may be used on workpiece carriers for micromechanical and semiconductor processing. One example includes a workpiece fitting to hold a workpiece when gripped by an electrostatic chucking force by an electrostatic chuck, an arm coupled to the workpiece fitting to pull the workpiece through the workpiece fitting laterally across the chuck, and a force gauge coupled to the arm to measure an amount of force with which the workpiece fitting is pulled by the arm in order to move the workpiece.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: December 29, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Gautam Pisharody, Seshadri Ramaswami, Shambhu N. Roy, Niranjan Kumar
  • Publication number: 20200385851
    Abstract: Embodiments of the present disclosure generally relate to a processing system for forming one or more layers of a photodiode. In one embodiment, the processing system includes a transfer chamber, a plurality of processing chambers, and a controller configured to cause a process to be performed in the processing system. The process includes performing a pre-clean process on a substrate, aligning and placing a first mask on the substrate, depositing a first layer on the substrate, and depositing a second layer on the substrate. The processing system can form layers of a photodiode in a low defect, cost effective, and high utilization manner.
    Type: Application
    Filed: May 1, 2020
    Publication date: December 10, 2020
    Inventors: Alexander N. LERNER, Roey SHAVIV, Michael P. KARAZIM, Kevin Vincent MORAES, Steven V. SANSONI, Andrew J. CONSTANT, Jeffrey Allen BRODINE, Kim Ramkumar VELLORE, Amikam SADE, Niranjan KUMAR
  • Patent number: 10665494
    Abstract: Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: May 26, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Niranjan Kumar, Seshadri Ramaswami, Shay Assaf, Amikam Sade, Andy Constant, Maureen Breiling
  • Patent number: 10645787
    Abstract: A system for providing electrical power to a load is provided. The system includes at least two inverters and at least two resonant circuits. The inverters are operative to electrically connect to a power source. The resonant circuits are each electrically connected to at least one of the inverters and operative to provide electrical power to the load. The resonant circuits are coupled to each other.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: May 5, 2020
    Assignee: General Electric Company
    Inventors: Philippe Ernest, Niranjan Kumar, Nicolas Levilly, Yash Veer Singh, Guillermo Garcia Soto
  • Publication number: 20190237352
    Abstract: Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 1, 2019
    Inventors: Niranjan KUMAR, Seshadri RAMASWAMI, Shay ASSAF, Amikam SADE, Andy CONSTANT, Maureen BREILING
  • Publication number: 20190211442
    Abstract: Substrate carrier apparatus having a hard mask are disclosed herein. In some embodiments, a substrate carrier apparatus includes a carrier body having a support surface to support a substrate; and a mask assembly disposed above the support surface. The mask assembly includes an annular frame disposed atop the support surface; and a hard mask coupled to and disposed within the annular frame above the support surface, wherein the hard mask includes one or more openings arranged in a predetermined pattern and disposed through the hard mask, and wherein the hard mask includes a plurality of spacer elements extending from a bottom surface of the hard mask.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 11, 2019
    Inventors: ALEXANDER LERNER, KIM VELLORE, AMI SADE, STEVEN SANSONI, ANDREW CONSTANT, KEVIN MORAES, ROEY SHAVIV, NIRANJAN KUMAR, JEFFREY BRODINE, MICHAEL KARAZIM
  • Publication number: 20190182944
    Abstract: A system for providing electrical power to a load is provided. The system includes at least two inverters and at least two resonant circuits. The inverters are operative to electrically connect to a power source. The resonant circuits are each electrically connected to at least one of the inverters and operative to provide electrical power to the load. The resonant circuits are coupled to each other.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 13, 2019
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: PHILIPPE ERNEST, NIRANJAN KUMAR, NICOLAS LEVILLY, YASH VEER SINGH, GUILLERMO GARCIA SOTO
  • Publication number: 20190115241
    Abstract: The present disclosure relates to an electrostatic chuck, including: a base having a dielectric first surface to support a substrate thereon during processing; and an electrode disposed within the base proximate the dielectric first surface to facilitate electrostatically coupling the substrate to the dielectric first surface during use, wherein the dielectric first surface is sufficiently hydrophobic to electrostatically retain the substrate to the dielectric first surface when contacted with water. Methods of making and using the electrostatic chuck under wet conditions are also disclosed.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 18, 2019
    Inventors: Kim VELLORE, Douglas A. BUCHBERGER, JR., Niranjan Kumar, Seshadri RAMASWAMI
  • Publication number: 20180374736
    Abstract: Embodiments of the disclosure relate to the use of an electrostatic carrier for securing, transporting and assembling dies on a substrate. In one embodiment, an electrostatic carrier includes a body having a top surface and a bottom surface, at least a first bipolar chucking electrode disposed within the body, at least two contact pads disposed on the bottom surface of the body and connected to the first bipolar chucking electrode, and a floating electrode disposed between the first bipolar chucking electrode and the bottom surface. In another embodiment, a die-assembling system includes the electrostatic carrier configured to electrostatically secure a plurality of dies, a carrier-holding platform configured to hold the electrostatic carrier, a die input platform and a loading robot having a range of motion configured to pick the plurality of dies from the die input platform and place them on the electrostatic carrier.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 27, 2018
    Inventors: Niranjan KUMAR, Kim Ramkumar VELLORE, Douglas H. BURNS, Gautam PISHARODY, Seshadri RAMASWAMI, Douglas A. BUCHBERGER, JR.
  • Publication number: 20180281151
    Abstract: Embodiments of the disclosure relate to a system, apparatus and method for polishing thin substrates with high planarity. The apparatus comprises a chemical mechanical polishing head and a plate. The polishing head comprises a bottom surface, a retaining ring, a workpiece-receiving pocket defined between the bottom surface and the retaining ring, and at least one vacuum port adapted to provide a vacuum to the workpiece-receiving pocket through the bottom surface of the polishing head. The plate is disposed in the workpiece-receiving pocket such that the upper side of the plate faces the bottom surface of the polishing head and the lower side of the plate faces away from the bottom surface of the polishing head. The plate has a geometry or a material property configured to allow fluid to pass between the upper side and the lower side of the plate upon application of vacuum in the workpiece-receiving pocket.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: Seshadri RAMASWAMI, Rajeev BAJAJ, Niranjan KUMAR, Sriskantharajah THIRUNAVUKARASU, Arvind SUNDARRAJAN
  • Publication number: 20180144959
    Abstract: An electrostatic chucking force tool is described that may be used on workpiece carriers for micromechanical and semiconductor processing. One example includes a workpiece fitting to hold a workpiece when gripped by an electrostatic chucking force by an electrostatic chuck, an arm coupled to the workpiece fitting to pull the workpiece through the workpiece fitting laterally across the chuck, and a force gauge coupled to the arm to measure an amount of force with which the workpiece fitting is pulled by the arm in order to move the workpiece.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 24, 2018
    Inventors: Srinivas D. Nemani, Gautam Pisharody, Seshadri Ramaswami, Shambhu N. Roy, Niranjan Kumar
  • Publication number: 20180122679
    Abstract: A substrate carrier with contacts is described that is balanced for thermal stress. In one example workpiece carrier has a rigid substrate configured to support a workpiece to be carried for processing, a first dielectric layer over the substrate, an electrostatic conductive electrode over the first dielectric layer to electrostatically hold the workpiece to be carried, a second dielectric layer over the electrode to electrically isolate the workpiece from the electrode, and a third dielectric layer under the substrate to counter thermal stress applied to the substrate by the first and second dielectric layers.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 3, 2018
    Inventors: Shambhu N. Roy, Gautam Pisharody, Seshadri Ramaswami, Srinivas D. Nemani, Zhong Qiang Hua, Douglas A. Buchberger, JR., Niranjan Kumar, Ellie Y. Yieh
  • Patent number: 9691543
    Abstract: A high voltage transformer arrangement for supplying power to a high voltage tank assembly is disclosed. The high voltage transformer arrangement includes a first core arranged in the high voltage tank assembly and a secondary winding configured on the first core, a second core positioned outside of the high voltage tank assembly and at a predefined distance from the first core, and a primary winding configured on the second core. The second core and the primary winding transfers current received from an external power source to the first core and secondary winding for supplying power to the high voltage tank assembly.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: June 27, 2017
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Niranjan Kumar, Dennis Perrillat-Amede, Venugopal Vadivel
  • Publication number: 20160262250
    Abstract: A power generation system includes an input to receive a low-voltage alternating current and a number N of voltage-conversion modules coupled to the input, each electrically connected in series. Each voltage-conversion module includes a transformer configured to convert the low-voltage alternating current into a high voltage alternating current. Each voltage-conversion module includes a multiplier configured to convert the high-voltage alternating current from the transformer into a high-voltage direct current. The multiplier includes a positive multiplier part and a negative multiplier part. The positive multiplier part and the negative multiplier part each includes a. pair of input terminals connected in parallel with the transform and at least one multiplier stage comprising a single diode and a capacitor assembly. The number N is an even number between 4 and 24.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Inventors: Saijun MAO, Denis Perrillat-Amede, Philippe Ernest, Niranjan Kumar, Xu Chu
  • Patent number: 9369060
    Abstract: A power generation system includes an input to receive a low-voltage alternating current and a number N of voltage-conversion modules coupled to the input, each electrically connected in series. Each voltage-conversion module includes a transformer configured to convert the low-voltage alternating current into a high-voltage alternating current. Each voltage-conversion module includes a multiplier configured to convert the high-voltage alternating current from the transformer into a high-voltage direct current. The multiplier includes a positive multiplier part and a negative multiplier part. The positive multiplier part and the negative multiplier part each includes a pair of input terminals connected in parallel with the transform and at least one multiplier stage comprising a single diode and a capacitor assembly. The number N is an even number between 4 and 24.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 14, 2016
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Saijun Mao, Denis Perrillat-Amede, Philippe Ernest, Niranjan Kumar, Xu Chu
  • Patent number: 9190899
    Abstract: A power circuit for protecting against high pulse load current and inrush current is disclosed. The power circuit comprises a buck-boost module and a PFC controller operatively coupled with the buck-boost module. The PFC controller is configured to receive an input voltage feedback, an output voltage feedback, and a current feedback, and is configured to utilize one of an Integral Gain Compensation (IGC) and an Integral Value Compensation (IVC) to control the high pulse load current and inrush current in the power circuit.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: November 17, 2015
    Assignee: General Electric Company
    Inventor: Niranjan Kumar