Abstract: Embodiments of the present disclosure generally relate to a processing system for forming one or more layers of a photodiode. In one embodiment, the processing system includes a transfer chamber, a plurality of processing chambers, and a controller configured to cause a process to be performed in the processing system. The process includes performing a pre-clean process on a substrate, aligning and placing a first mask on the substrate, depositing a first layer on the substrate, and depositing a second layer on the substrate. The processing system can form layers of a photodiode in a low defect, cost effective, and high utilization manner.

Abstract: Apparatus and method for memoizing repeat function calls are described herein. An apparatus embodiment includes: uop buffer circuitry to identify a function for memoization based on retiring micro-operations (uops) from a processing pipeline; memoization retirement circuitry to generate a signature of the function which includes input and output data of the function; a memoization data structure to store the signature; and predictor circuitry to detect an instance of the function to be executed by the processing pipeline and to responsively exclude a first subset of uops associated with the instance from execution when a confidence level associated with the function is above a threshold. One or more instructions that are data-dependent on execution of the instance is then provided with the output data of the function from the memoization data structure.

Abstract: In one embodiment, a processor includes: a decode circuit to decode a branch instruction, the branch instruction comprising a hint field to provide spatial information regarding a distance between the branch instruction and a target instruction of the branch instruction; a branch predictor to predict whether the branch instruction is to be taken; and a branch target buffer (BTB) coupled to the branch predictor. The BTB, based at least in part on the spatial information, may allocate an entry for the branch instruction in one of a first portion of the BTB and a second portion of the BTB. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes a branch predictor to predict whether a branch instruction is to be taken and a branch target buffer (BTB) coupled to the branch predictor. The branch target buffer may be segmented into a first cache portion and a second cache portion, where, in response to an indication that the branch is to be taken, the BTB is to access an entry in one of the first cache portion and the second cache portion based at least in part on a type of the branch instruction, an occurrence frequency of the branch instruction, and spatial information regarding a distance between a target address of a target of the branch instruction and an address of the branch instruction. Other embodiments are described and claimed.

Abstract: A system for automatically constructing a flight plan that aligns with a boundary line is provided. The system has a controller that is configured to: automatically select a set of geographical (geo) coordinate waypoints along a boundary line using waypoints from the geographical database responsive to flight crew input; refine the set of geo coordinate waypoints using a calculated turn initiation distance and a turn completion distance for every waypoint; further refine the refined set of geo coordinate waypoints based on the course change between waypoints; generate a set of courses and distances between waypoints through computing, for each set of two consecutive waypoints in the further refined set of geo coordinate waypoints, the course and distance between the two consecutive waypoints; and construct the flight plan based on the waypoints in the further refined set of geo coordinate waypoints and the set of courses and distances between waypoints.

Abstract: Methods and apparatus relating to branch prefetch mechanisms for mitigating frontend branch resteers are described. In an embodiment, predecodes an entry in a cache to generate a predecoded branch operation. The entry is associated with a cold branch operation, where the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line. The predecoded branch operation is stored in a Branch Prefetch Buffer (BPB) in response to a cache line fill operation of the cold branch operation in an instruction cache. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to Instruction Set Architecture (ISA) and/or microarchitecture for early pipeline re-steering using load address prediction to mitigate branch misprediction penalties are described. In an embodiment, decode circuitry decodes a load instruction and Load Address Predictor (LAP) circuitry issues a load prefetch request to memory for data for a load operation of the load instruction. Compute circuitry executes an outcome for a branch operation of the load instruction based on the data from the load prefetch request. And re-steering circuitry transmits a signal to cause flushing of data associated with the load instruction in response to a mismatch between the outcome for the branch operation and a stored prediction value for the branch. Other embodiments are also disclosed and claimed.

Abstract: A system for automatically constructing a flight plan that aligns with a boundary line is provided. The system has a controller that is configured to: automatically select a set of geographical (geo) coordinate waypoints along a boundary line using waypoints from the geographical database responsive to flight crew input; refine the set of geo coordinate waypoints using a calculated turn initiation distance and a turn completion distance for every waypoint; further refine the refined set of geo coordinate waypoints based on the course change between waypoints; generate a set of courses and distances between waypoints through computing, for each set of two consecutive waypoints in the further refined set of geo coordinate waypoints, the course and distance between the two consecutive waypoints; and construct the flight plan based on the waypoints in the further refined set of geo coordinate waypoints and the set of courses and distances between waypoints.

Abstract: Substrate carrier apparatus having a hard mask are disclosed herein. In some embodiments, a substrate carrier apparatus includes a carrier body having a support surface to support a substrate; and a mask assembly disposed above the support surface. The mask assembly includes an annular frame disposed atop the support surface; and a hard mask coupled to and disposed within the annular frame above the support surface, wherein the hard mask includes one or more openings arranged in a predetermined pattern and disposed through the hard mask, and wherein the hard mask includes a plurality of spacer elements extending from a bottom surface of the hard mask.

Abstract: An electrostatic chucking force tool is described that may be used on workpiece carriers for micromechanical and semiconductor processing. One example includes a workpiece fitting to hold a workpiece when gripped by an electrostatic chucking force by an electrostatic chuck, an arm coupled to the workpiece fitting to pull the workpiece through the workpiece fitting laterally across the chuck, and a force gauge coupled to the arm to measure an amount of force with which the workpiece fitting is pulled by the arm in order to move the workpiece.

Abstract: Embodiments of the present disclosure generally relate to a processing system for forming one or more layers of a photodiode. In one embodiment, the processing system includes a transfer chamber, a plurality of processing chambers, and a controller configured to cause a process to be performed in the processing system. The process includes performing a pre-clean process on a substrate, aligning and placing a first mask on the substrate, depositing a first layer on the substrate, and depositing a second layer on the substrate. The processing system can form layers of a photodiode in a low defect, cost effective, and high utilization manner.

Abstract: Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.

Abstract: A system for providing electrical power to a load is provided. The system includes at least two inverters and at least two resonant circuits. The inverters are operative to electrically connect to a power source. The resonant circuits are each electrically connected to at least one of the inverters and operative to provide electrical power to the load. The resonant circuits are coupled to each other.

Abstract: Methods of identifying target binding molecules by target guided synthesis are provided. The methods include providing two or more fragments capable of reacting to form the target binding molecule and mixing the fragments with the target. The methods can be used to identify target binding molecules that bind targets such as proteins or nucleic acids, including those that bind shallow binding pockets on the surface of such targets. The methods are applied to the Bcl-XL and Mcl-1 proteins from the Bcl-2 family of proteins. Using thio acid and sulfonyl azide fragments capable of reacting through sulfo-click chemistry, new acyl sulfonamides are identified that bind one or both of the Bcl-XL and Mcl-1 proteins. Pharmaceutical formulations of these target binding molecules are also provided.

Abstract: Formulations of the HIV compounds atazanavir and cobicistat, and methods of treatment utilizing these formulations, are set forth.

Abstract: Embodiments include a method for processing thin substrates. Embodiments may include electrostatically bonding a substrate to a first electrostatic carrier (ESC), with a backside of the substrate is facing away from the first ESC. Thereafter, the substrate may be thinned to form a thinned substrate. The thinned substrate may then be transferred to a second ESC with a front side of the thinned substrate facing away from the second ESC. Embodiments may include cleaning the front side surface of the thinned substrate and transferring the thinned substrate to a third ESC. In an embodiment, a backside of the thinned substrate is facing away from the third ESC. Embodiments may also include processing the backside surface of the thinned substrate, and transferring the thinned substrate to a tape frame.

Abstract: Substrate carrier apparatus having a hard mask are disclosed herein. In some embodiments, a substrate carrier apparatus includes a carrier body having a support surface to support a substrate; and a mask assembly disposed above the support surface. The mask assembly includes an annular frame disposed atop the support surface; and a hard mask coupled to and disposed within the annular frame above the support surface, wherein the hard mask includes one or more openings arranged in a predetermined pattern and disposed through the hard mask, and wherein the hard mask includes a plurality of spacer elements extending from a bottom surface of the hard mask.

Abstract: A system for providing electrical power to a load is provided. The system includes at least two inverters and at least two resonant circuits. The inverters are operative to electrically connect to a power source. The resonant circuits are each electrically connected to at least one of the inverters and operative to provide electrical power to the load. The resonant circuits are coupled to each other.

Abstract: The present disclosure relates to an electrostatic chuck, including: a base having a dielectric first surface to support a substrate thereon during processing; and an electrode disposed within the base proximate the dielectric first surface to facilitate electrostatically coupling the substrate to the dielectric first surface during use, wherein the dielectric first surface is sufficiently hydrophobic to electrostatically retain the substrate to the dielectric first surface when contacted with water. Methods of making and using the electrostatic chuck under wet conditions are also disclosed.

Abstract: Embodiments of the disclosure relate to the use of an electrostatic carrier for securing, transporting and assembling dies on a substrate. In one embodiment, an electrostatic carrier includes a body having a top surface and a bottom surface, at least a first bipolar chucking electrode disposed within the body, at least two contact pads disposed on the bottom surface of the body and connected to the first bipolar chucking electrode, and a floating electrode disposed between the first bipolar chucking electrode and the bottom surface. In another embodiment, a die-assembling system includes the electrostatic carrier configured to electrostatically secure a plurality of dies, a carrier-holding platform configured to hold the electrostatic carrier, a die input platform and a loading robot having a range of motion configured to pick the plurality of dies from the die input platform and place them on the electrostatic carrier.