Patents by Inventor Niranjay Ravindran

Niranjay Ravindran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220376711
    Abstract: Example systems, read channels, and methods provide bit value detection from an encoded data signal using a neural network soft information detector. The neural network detector determines a set of probabilities for possible states of a data symbol from the encoded data signal. A soft output detector uses the set of probabilities for possible states of the data symbol to determine a set of bit probabilities that are iteratively exchanged as extrinsic information with an iterative decoder for making decoding decisions. The iterative decoder outputs decoded bit values for a data unit that includes the data symbol.
    Type: Application
    Filed: September 21, 2021
    Publication date: November 24, 2022
    Inventors: Iouri Oboukhov, Daniel Bedau, Richard Galbraith, Niranjay Ravindran, Weldon Hanson, Pradhan Bellam
  • Patent number: 11487611
    Abstract: The present disclosure generally relates to applying LDPC coding to memory cells with an arbitrary number of levels. Modulation code is applied to a first portion of user bits. The coded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block different from the first modulation block. Modulation code is then applied to a second portion of user bits which are stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a separate modulation block from the modulation block where the user data is stored.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran
  • Publication number: 20220283950
    Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.
    Type: Application
    Filed: May 17, 2022
    Publication date: September 8, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Bernie RUB, Mostafa EL GAMAL, Niranjay RAVINDRAN, Richard David BARNDT, Henry CHIN, Ravi J. KUMAR, James FITZPATRICK
  • Patent number: 11411584
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A first block of data is channel encoded into first channel data based on a channel code constraint, and the first channel data is error correction encoded to generate first redundancy bits. A second block of data is channel encoded into second channel data based on the channel code constraint and the first redundancy bits, and the first channel data and the second channel data are error correction encode to generate second redundancy bits. A third block of data is channel encoded into third channel data based on the channel code constraint and the second redundancy bits. The first, second and third channel data and the first and second redundancy bits are stored in the NVSM.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: August 9, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Iouri Oboukhov, Richard L. Galbraith, Niranjay Ravindran
  • Patent number: 11372765
    Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 28, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Bernie Rub, Mostafa El Gamal, Niranjay Ravindran, Richard David Barndt, Henry Chin, Ravi J. Kumar, James Fitzpatrick
  • Publication number: 20220107865
    Abstract: The present disclosure generally relates to applying LDPC coding to memory cells with an arbitrary number of levels. Modulation code is applied to a first portion of user bits. The coded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block different from the first modulation block. Modulation code is then applied to a second portion of user bits which are stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a separate modulation block from the modulation block where the user data is stored.
    Type: Application
    Filed: February 23, 2021
    Publication date: April 7, 2022
    Inventors: Iouri OBOUKHOV, Richard GALBRAITH, Jonas GOODE, Niranjay RAVINDRAN
  • Publication number: 20220103188
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A first block of data is channel encoded into first channel data based on a channel code constraint, and the first channel data is error correction encoded to generate first redundancy bits. A second block of data is channel encoded into second channel data based on the channel code constraint and the first redundancy bits, and the first channel data and the second channel data are error correction encode to generate second redundancy bits. A third block of data is channel encoded into third channel data based on the channel code constraint and the second redundancy bits. The first, second and third channel data and the first and second redundancy bits are stored in the NVSM.
    Type: Application
    Filed: February 19, 2021
    Publication date: March 31, 2022
    Inventors: IOURI OBOUKHOV, RICHARD L. GALBRAITH, NIRANJAY RAVINDRAN
  • Patent number: 11289123
    Abstract: An external servo writer configured to write a plurality of embedded servo sectors on a magnetic tape to define a plurality of data tracks is disclosed. A first part of the plurality of embedded servo sectors is written while controlling an actuator to first move a head vertically along a width of the magnetic tape. A second part of the plurality of embedded servo sectors is written while controlling the actuator to second move the head vertically along the width of the magnetic tape.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: March 29, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Derrick E. Burton, Niranjay Ravindran, Iouri Oboukhov
  • Publication number: 20210350825
    Abstract: An external servo writer configured to write a plurality of embedded servo sectors on a magnetic tape to define a plurality of data tracks is disclosed. A first part of the plurality of embedded servo sectors is written while controlling an actuator to first move a head vertically along a width of the magnetic tape. A second part of the plurality of embedded servo sectors is written while controlling the actuator to second move the head vertically along the width of the magnetic tape.
    Type: Application
    Filed: June 17, 2021
    Publication date: November 11, 2021
    Inventors: RICHARD L. GALBRAITH, WELDON M. HANSON, DERRICK E. BURTON, NIRANJAY RAVINDRAN, IOURI OBOUKHOV
  • Publication number: 20210327504
    Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Mostafa EL GAMAL, Niranjay RAVINDRAN, James FITZPATRICK
  • Publication number: 20210319837
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
  • Patent number: 11138996
    Abstract: A data storage device is disclosed comprising at least one head configured to access a magnetic tape comprising a plurality of data tracks, wherein each data track comprises a plurality of data segments and a plurality of servo sectors. The head is used to read one of the servo sectors to generate a first read signal. The first read signal is processed to generate a position error signal (PES) of the head relative to the magnetic tape, wherein the head is positioned relative to the magnetic tape based on the PES. The head is used to read one of the data segments to generate a second read signal, wherein the second read signal is processed to detect user data recorded in the data segment.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: October 5, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Derrick E. Burton, Niranjay Ravindran, Iouri Oboukhov
  • Patent number: 11107522
    Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: August 31, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mostafa El Gamal, Niranjay Ravindran, James Fitzpatrick
  • Patent number: 11101006
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 24, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
  • Patent number: 11055171
    Abstract: A data storage device is disclosed comprising a head actuated over a disk. A first plurality of codewords and corresponding parity sector are generated, and a second plurality of codewords and corresponding parity sector are generated. The first and second plurality of codewords are written to the disk, and during a read of the first and second set of codewords, M codeword locations within the data track that are unrecoverable are saved, and N codeword locations out of the M codeword locations are selected based on a quality metric of the read. The N codewords are reread from the data track at the N codeword locations and reliability metrics associated with the N codewords are saved. The saved reliability metrics are updated using at least one of the first parity sector or the second parity sector.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niranjay Ravindran, Weldon M. Hanson, Richard L. Galbraith, David T. Flynn, Iouri Oboukhov
  • Patent number: 11049520
    Abstract: A data storage device is disclosed comprising at least one head configured to access a magnetic tape. Data is read from the magnetic tape to generate a read signal which is processed to decode a first M blocks of low density parity check (LDPC) type codewords using a LDPC type decoder. First un-converged codewords out of the first M blocks are decoded using a first M-blocks parity, and second un-converged codewords out of the first M blocks are decoded using an erasure code.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: June 29, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard L. Galbraith, Weldon M. Hanson, Derrick E. Burton, Niranjay Ravindran, Iouri Oboukhov
  • Publication number: 20210175903
    Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN
  • Patent number: 10990295
    Abstract: The disclosure relates in some aspects to optimizing writes levels used for programming a non-volatile memory device. In some aspects, the disclosure relates to an algorithmic approach for adjusting write levels for a NAND flash device. For example, write level gradients may be iteratively generated based on memory cell bin distribution statistics relating to the number and direction of errors across bin boundaries.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: April 27, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard Leo Galbraith, Niranjay Ravindran, Jonas Andrew Goode
  • Patent number: 10965321
    Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran
  • Patent number: 10937510
    Abstract: A method for identifying cell coupling in a memory system includes generating a two-dimensional pseudorandom binary sequence array. The method also includes performing an erase operation on a plurality of cells of a memory block of the memory system. The method also includes performing a write operation on the plurality of cells using the two-dimensional pseudorandom binary sequence array. The method also includes performing a read operation on the plurality of cells to identify a voltage value for each cell of the plurality of cells. The method also includes identifying cell coupling between respective cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard Galbraith, Jonas Goode, Henry Yip, Ravi Kumar, Niranjay Ravindran