Abstract: Example systems and methods for using a multi-tier error correction code distributed among oligos for DNA data storage are described. A data unit is encoded as a set of codewords where each codeword is distributed as symbols on different oligos. The codewords include a set of first tier codewords that include CRC and ECC redundancy data and one or more additional tiers of codewords that include permuted data and corresponding ECC redundancy data. Decoding includes a sequence of decoding iterations between the first tier of codewords and additional tiers of codewords.

Abstract: Example systems and methods for embedding an oligo index in a series of reference marks along the oligo for DNA data storage are described. A data unit may be encoded in oligos that include reference marks at predetermined intervals along the length of each oligo that encode the oligo index, generally in multiple copies encoded with varying symmetries. During decoding, the reference marks may be analyzed through multiple correlation matrices to determine a most likely set of values for the oligo index. In some configurations, the same reference marks may be processed through another correlation matrix to determine and correct insertions and deletions based on multiple copies of the oligo, as identified by the decoded oligo indices in those copies.

Abstract: Example systems and methods for using synchronization marks to correct insertions and deletions for DNA data storage are described. A data unit may be encoded in oligos that include synchronization marks at predetermined intervals along the length of each oligo. During decoding, the synchronization marks may improve identification and isolation of insertions and deletions for correction of symbol alignment prior to error correction code decoding. In some configurations, correlation analysis may be used to improve isolation of insertions and deletions where multiple copies of the same oligo are available.

Abstract: Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

Abstract: Example systems and methods for using nested error correction codes for DNA data storage are described. A data unit may be encoded in a set of oligos. Using an error correction code, such as an LDPC code, a codeword may be determined for the data unit that is a multiple of the data payload capacity of each oligo. The codeword may be divided among the set of oligos, along with corresponding redundancy data. Any number of additional levels of nested error correction codes may be implemented by aggregating sets of smaller codewords into larger codewords and storing the corresponding redundancy data in the set of oligos. Each nested level may be aggregated from the set of oligos and decoded using the corresponding error correction code matrix and set of redundancy data as needed, such as in response to failure to decode codewords at a lower level.

Abstract: Example channel circuits, data storage devices, and methods for using zero force adaptation to equalize a read data signal based on known data are described. A known user data signal may be determined during prior read operations and used with a residue term from the equalized read data signal to adapt the tap weights for an equalizer filter using a zero force adaptation algorithm. For example, the known user data signal may be determined by a soft output detector (e.g., SOVA detector) or full or partial decoding by an iterative decoder (e.g., LDPC decoder) and fed back for adapting the equalizer.

Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. Mutual information metrics may be calculated based on a multi-bit symbol size to compensate for inter-symbol interference and compared to mutual information thresholds to determine the configuration settings, such as bit and track densities, error correction codes, and modulation codes. Mutual information metrics may be used to characterize heads and media independent of the configuration settings.

Abstract: Example systems, read channel circuits, data storage devices, and methods to use a global variance parameter based on mutual information to modify operation of a soft output detector in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector that includes variance terms. The variance terms are modified by a global variance parameter based on mutual information values. The soft output detector processes an input signal using the modified branch variance terms to determine data bits and corresponding soft information for decoding data in the read channel.

Abstract: Example channel circuits, data storage devices, and methods for using zero force adaptation to equalize a read data signal based on known data are described. A known user data signal may be determined during prior read operations and used with a residue term from the equalized read data signal to adapt the tap weights for an equalizer filter using a zero force adaptation algorithm. For example, the known user data signal may be determined by a soft output detector (e.g., SOVA detector) or full or partial decoding by an iterative decoder (e.g., LDPC decoder) and fed back for adapting the equalizer.

Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using symbol context mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. The configuration settings may be determined by determining a known pattern for a sector, determining a series of symbol contexts, determining mutual information for each symbol context, and using the symbol context mutual information to determine relationships among configuration settings, such as bit size, error correction code rate, and modulation code. Once determined, the configuration settings may be used to configure the modulation code and ECC rate for the channel circuit of the data storage device.

Abstract: Example systems and methods for using a multi-tier error correction code distributed among oligos for DNA data storage are described. A data unit may be encoded as a set of codewords where each codeword is distributed as symbols on different oligos. The codewords may include a set of first tier codewords that include CRC and ECC redundancy data and one or more additional tiers of codewords that include permuted data and corresponding ECC redundancy data. Decoding may include a sequence of decoding iterations between the first tier of codewords and additional tiers of codewords.

Abstract: Example channel circuits, data storage devices, and methods for data read synchronization from phase modulated synchronization fields are described. A data synchronization detector may receive an oversampled digital read signal read from a synchronization field that uses a single written pattern to encode the start of data position, phase, and gain for the read channel. The write pattern may use a phase modulated carrier signal to encode a pseudo-random binary sequence indicating the start of data position.

Abstract: Example channel circuits, data storage devices, and methods for data read synchronization from phase modulated synchronization fields are described. A data synchronization detector may receive an oversampled digital read signal read from a synchronization field that uses a single written pattern to encode the start of data position, phase, and gain for the read channel. The write pattern may use a phase modulated carrier signal to encode a pseudo-random binary sequence indicating the start of data position.

Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.

Abstract: Example systems, read channel circuits, data storage devices, and methods to use a global variance parameter based on mutual information to modify operation of a soft output detector in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector that includes variance terms. The variance terms are modified by a global variance parameter based on mutual information values. The soft output detector processes an input signal using the modified branch variance terms to determine data bits and corresponding soft information for decoding data in the read channel.

Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. Mutual information metrics may be calculated based on a multi-bit symbol size to compensate for inter-symbol interference and compared to mutual information thresholds to determine the configuration settings, such as bit and track densities, error correction codes, and modulation codes. Mutual information metrics may be used to characterize heads and media independent of the configuration settings.

Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using symbol context mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. The configuration settings may be determined by determining a known pattern for a sector, determining a series of symbol contexts, determining mutual information for each symbol context, and using the symbol context mutual information to determine relationships among configuration settings, such as bit size, error correction code rate, and modulation code. Once determined, the configuration settings may be used to configure the modulation code and ECC rate for the channel circuit of the data storage device.

Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.

Abstract: Example systems, read channels, and methods provide multiple neural network training nodes for processing read data signals prior to symbol detection and decoding. A plurality of neural network circuits receive read data signals and modify them based on different neural network configurations and sets of trained node coefficients. Each neural network circuit may pass modified read data signals directly to another neural network circuit or determine a parameter for modifying processing of the read data signals by another component. In some configurations, the last neural network circuit may pass the output read data signal to a soft output detector for determining the symbols in the read data signal.

Abstract: Various illustrative aspects are directed to a data storage device comprising data tracks N and N?1, and one or more processing devices, configured to identify, during a track write on the data track N, a write abort event based upon an expected risk for the data track N?1 exceeding a risk threshold, read one or more sectors of the data track N?1 and collect one or more corresponding sector metrics, verify the one or more sectors based upon the collected sector metrics, wherein the verifying comprises assigning each of the one or more sectors as one of a readable or a non-readable sector, and continue the track write on the data track N upon determining each of the one or more sectors is a readable sector, or recovering and relocating the data track N?1 based on determining at least one of the sectors is a non-readable sector.