Patents by Inventor Niranjay Ravindran

Niranjay Ravindran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12099409
    Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: September 24, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Derrick Burton, Weldon M. Hanson, Richard Galbraith, Niranjay Ravindran
  • Publication number: 20240265943
    Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. Mutual information metrics may be calculated based on a multi-bit symbol size to compensate for inter-symbol interference and compared to mutual information thresholds to determine the configuration settings, such as bit and track densities, error correction codes, and modulation codes. Mutual information metrics may be used to characterize heads and media independent of the configuration settings.
    Type: Application
    Filed: December 6, 2023
    Publication date: August 8, 2024
    Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran, Jihoon Park
  • Publication number: 20240264765
    Abstract: Example systems, read channel circuits, data storage devices, and methods to use a global variance parameter based on mutual information to modify operation of a soft output detector in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector that includes variance terms. The variance terms are modified by a global variance parameter based on mutual information values. The soft output detector processes an input signal using the modified branch variance terms to determine data bits and corresponding soft information for decoding data in the read channel.
    Type: Application
    Filed: July 19, 2023
    Publication date: August 8, 2024
    Inventors: Richard Galbraith, Iouri Oboukhov, Jonas Goode, Niranjay Ravindran, Pradhan Bellam, Henry Yip
  • Publication number: 20240265948
    Abstract: Example systems, data storage devices, testers, and methods for storage device configuration using symbol context mutual information are described. A data storage device may include channel circuit configuration settings for the encoding and decoding of data written to a non-volatile storage medium. The configuration settings may be determined by determining a known pattern for a sector, determining a series of symbol contexts, determining mutual information for each symbol context, and using the symbol context mutual information to determine relationships among configuration settings, such as bit size, error correction code rate, and modulation code. Once determined, the configuration settings may be used to configure the modulation code and ECC rate for the channel circuit of the data storage device.
    Type: Application
    Filed: December 6, 2023
    Publication date: August 8, 2024
    Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Niranjay Ravindran, Jihoon Park
  • Patent number: 12028091
    Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: July 2, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Derrick E. Burton, Weldon M. Hanson, Niranjay Ravindran, Richard Galbraith, Jonas Goode
  • Publication number: 20240211729
    Abstract: Example systems, read channels, and methods provide multiple neural network training nodes for processing read data signals prior to symbol detection and decoding. A plurality of neural network circuits receive read data signals and modify them based on different neural network configurations and sets of trained node coefficients. Each neural network circuit may pass modified read data signals directly to another neural network circuit or determine a parameter for modifying processing of the read data signals by another component. In some configurations, the last neural network circuit may pass the output read data signal to a soft output detector for determining the symbols in the read data signal.
    Type: Application
    Filed: July 19, 2023
    Publication date: June 27, 2024
    Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Henry Yip, Niranjay Ravindran
  • Patent number: 12020733
    Abstract: Various illustrative aspects are directed to a data storage device comprising data tracks N and N?1, and one or more processing devices, configured to identify, during a track write on the data track N, a write abort event based upon an expected risk for the data track N?1 exceeding a risk threshold, read one or more sectors of the data track N?1 and collect one or more corresponding sector metrics, verify the one or more sectors based upon the collected sector metrics, wherein the verifying comprises assigning each of the one or more sectors as one of a readable or a non-readable sector, and continue the track write on the data track N upon determining each of the one or more sectors is a readable sector, or recovering and relocating the data track N?1 based on determining at least one of the sectors is a non-readable sector.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: June 25, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niranjay Ravindran, Weldon M. Hanson, Hiroyasu Masuda, David T. Flynn, Zarko Popov
  • Publication number: 20240185959
    Abstract: Example systems and methods for using nested error correction codes for DNA data storage are described. A data unit may be encoded in a set of oligos. Using an error correction code, such as an LDPC code, a codeword may be determined for the data unit that is a multiple of the data payload capacity of each oligo. The codeword may be divided among the set of oligos, along with corresponding redundancy data. Any number of additional levels of nested error correction codes may be implemented by aggregating sets of smaller codewords into larger codewords and storing the corresponding redundancy data in the set of oligos. Each nested level may be aggregated from the set of oligos and decoded using the corresponding error correction code matrix and set of redundancy data as needed, such as in response to failure to decode codewords at a lower level.
    Type: Application
    Filed: November 1, 2023
    Publication date: June 6, 2024
    Inventors: Iouri Oboukhov, Richard Galbraith, Niranjay Ravindran, Jonas Goode, Weldon M. Hanson
  • Publication number: 20240184666
    Abstract: Example systems and methods for using synchronization marks to correct insertions and deletions for DNA data storage are described. A data unit may be encoded in oligos that include synchronization marks at predetermined intervals along the length of each oligo. During decoding, the synchronization marks may improve identification and isolation of insertions and deletions for correction of symbol alignment prior to error correction code decoding. In some configurations, correlation analysis may be used to improve isolation of insertions and deletions where multiple copies of the same oligo are available.
    Type: Application
    Filed: November 1, 2023
    Publication date: June 6, 2024
    Inventors: Iouri Oboukhov, Richard Galbraith, Niranjay Ravindran, Jonas Goode, Weldon M. Hanson
  • Patent number: 11953987
    Abstract: Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 9, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Henry Yip, Niranjay Ravindran
  • Patent number: 11948602
    Abstract: Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: April 2, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Weldon M. Hanson, Richard Galbraith, Iouri Oboukhov, Niranjay Ravindran, Derrick Burton
  • Publication number: 20240106461
    Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Iouri Oboukhov, Derrick E. Burton, Weldon M. Hanson, Niranjay Ravindran, Richard Galbraith, Jonas Goode
  • Publication number: 20240097696
    Abstract: Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.
    Type: Application
    Filed: July 18, 2023
    Publication date: March 21, 2024
    Inventors: Richard Galbraith, Michael J. Ross, Weldon M. Hanson, John T. Contreras, Iouri Oboukhov, Niranjay Ravindran, Pradhan Bellam, Derrick E. Burton
  • Publication number: 20240095121
    Abstract: Example systems, read channels, and methods provide states equalization for a digital data signal in preparation for a soft output detector. The states equalizer determines a set of signal values from the digital data signal and filters the set of signal values through a set of finite impulse response filters configured to generate a set of state values for a target signal value, where each filter corresponds to a potential state of the target signal value. Based on the state values, a set of probabilities for possible states is determined and used to populate a decision matrix for a soft output detector.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Iouri Oboukhov, Richard Galbraith, Jonas Goode, Henry Yip, Niranjay Ravindran
  • Patent number: 11929093
    Abstract: Example read channel circuits, data storage devices, and methods to provide overlapping processing of data tracks are described. The data storage device may include media configured with a plurality of tracks in a concentric or continuous pattern. The read signal for a data track may be processed using error correction codes (ECC) as it is read during a first track read operation period. Some portion of its data sectors may need additional ECC postprocessing after the first track is initially received and processed by the read channel circuit. While the read signal for a next data track is being read and processed, the read channel circuit may continue postprocessing of the portion of data sectors from the first track during the second track read operations. Various decision parameters for managing the data stream, additional postprocessing time, and rereading tracks for data recovery are also described.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 12, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Weldon M. Hanson, Niranjay Ravindran, Richard Galbraith, Iouri Oboukhov
  • Publication number: 20240005959
    Abstract: Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Weldon M. Hanson, Richard Galbraith, Iouri Oboukhov, Niranjay Ravindran, Derrick Burton
  • Publication number: 20230393937
    Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Iouri Oboukhov, Derrick Burton, Weldon M. Hanson, Richard Galbraith, Niranjay Ravindran
  • Patent number: 11811425
    Abstract: Example systems, read channels, and methods provide bit value detection from an encoded data signal using a neural network soft information detector. The neural network detector determines a set of probabilities for possible states of a data symbol from the encoded data signal. A soft output detector uses the set of probabilities for possible states of the data symbol to determine a set of bit probabilities that are iteratively exchanged as extrinsic information with an iterative decoder for making decoding decisions. The iterative decoder outputs decoded bit values for a data unit that includes the data symbol.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Daniel Bedau, Richard Galbraith, Niranjay Ravindran, Weldon Hanson, Pradhan Bellam
  • Publication number: 20230335158
    Abstract: Various illustrative aspects are directed to a data storage device comprising data tracks N and N?1, and one or more processing devices, configured to identify, during a track write on the data track N, a write abort event based upon an expected risk for the data track N?1 exceeding a risk threshold, read one or more sectors of the data track N?1 and collect one or more corresponding sector metrics, verify the one or more sectors based upon the collected sector metrics, wherein the verifying comprises assigning each of the one or more sectors as one of a readable or a non-readable sector, and continue the track write on the data track N upon determining each of the one or more sectors is a readable sector, or recovering and relocating the data track N?1 based on determining at least one of the sectors is a non-readable sector.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 19, 2023
    Inventors: Niranjay Ravindran, Weldon M. Hanson, Hiroyasu Masuda, David T. Flynn, Zarko Popov
  • Publication number: 20230306994
    Abstract: Various illustrative aspects are directed to a data storage device comprising data tracks N and N?1, and one or more processing devices, configured to measure signal to noise ratio (SNR) metrics for corresponding sectors of at least one of the data tracks N?1 and N, where the measuring is based at least in part on reading one or more of the data tracks N and N?1 using one or more read offsets, estimate a position of at least one of the data tracks based on measuring the one or more SNR metrics, and reconstruct one or more of risk values for at least a portion of the data track N?1 based on the one or more SNR metrics for the data track N?1, and a position error signal (PES) for at least one of the data tracks N?1 and N based on the corresponding estimated positions.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Inventors: Weldon M. Hanson, Alain Chahwan, Niranjay Ravindran