Patents by Inventor Niranjay Ravindran

Niranjay Ravindran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190384504
    Abstract: The disclosure relates in some aspects to optimizing writes levels used for programming a non-volatile memory device. In some aspects, the disclosure relates to an algorithmic approach for adjusting write levels for a NAND flash device. For example, write level gradients may be iteratively generated based on memory cell bin distribution statistics relating to the number and direction of errors across bin boundaries.
    Type: Application
    Filed: October 11, 2018
    Publication date: December 19, 2019
    Inventors: Richard Leo Galbraith, Niranjay Ravindran, Jonas Andrew Goode
  • Publication number: 20190356334
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a data track having at least a first data segment and a second data segment. A first plurality of codewords are generated, and a first parity sector is generated over the first plurality of codewords. The first plurality of codewords and the first parity sector are written to the first data segment. A second plurality of codewords are generated, and a second parity sector is generated over the second plurality of codewords. The second plurality of codewords and the second parity sector are written to the second data segment. During a read operation the data segments of the data track are processed sequentially to decode the codewords using a low density parity check (LDPC) decoder, wherein the reliability metrics of un-converged codewords are stored in a codeword buffer and updated using the respective parity sector.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: IOURI OBOUKHOV, WELDON M. HANSON, NIRANJAY RAVINDRAN, RICHARD L. GALBRAITH
  • Publication number: 20190354430
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM), wherein a plurality of codewords and corresponding parity sector are written to the NVSM and then read from the NVSM. Each codeword read from the NVSM is processed using a Viterbi-type detector, thereby generating codeword reliability metrics. The codeword reliability metrics for at least some of the codewords are processed using a low density parity check (LDPC) type decoder, thereby generating a LDPC reliability metric for each symbol of at least one codeword. The LDPC reliability metrics for at least one of an un-converged codeword are processed using the parity sector, thereby updating the un-converged codeword reliability metrics. Processing the codeword reliability metrics with the LDPC decoder and updating the reliability metrics with the parity sector is repeated at least once before updating the LDPC reliability metrics of at least the un-converged codeword using the Viterbi-type detector.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: IOURI OBOUKHOV, NIRANJAY RAVINDRAN, RICHARD L. GALBRAITH
  • Publication number: 20190354434
    Abstract: A data storage device is disclosed wherein a first plurality of codewords are generated each comprising a plurality of symbols, and a first parity sector is generated over the first plurality of codewords. A second plurality of codewords are generated each comprising a plurality of symbols, and a second parity sector is generated over the second plurality of codewords. A third parity sector is generated over a first subset of the first plurality of codewords and a first subset of the second plurality of codewords, and a fourth parity sector is generated over a second subset of the first plurality of codewords and a second subset of the second plurality of codewords. When processing of a first codeword fails, the first codeword and the first parity sector are processed using a LDPC type decoder, and the first codeword and the third parity sector are processed using the LDPC type decoder.
    Type: Application
    Filed: January 10, 2019
    Publication date: November 21, 2019
    Inventors: IOURI OBOUKHOV, WELDON M. HANSON, NIRANJAY RAVINDRAN, DAVID T. FLYNN
  • Patent number: 10417089
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A reliability metric for each symbol of each of a plurality of codewords read from the NVSM is generated, and a number of erasures for a first codeword are generated, wherein the number of erasures exceeds the correction power of the first codeword. A reliability metric of the first codeword is modified corresponding to one of the erasures. The reliability metrics for each codeword including the modified reliability metrics of the first codeword are first iteratively processed using a low density parity check (LDPC) type decoder, thereby first updating the reliability metric for each symbol of each codeword. The reliability metrics for the first codeword are second updated using the parity sector, and the second updated reliability metrics for the first codeword are second iteratively processed using the LDPC-type decoder.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 17, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Iouri Oboukhov, Weldon M. Hanson, Niranjay Ravindran, Richard L. Galbraith
  • Patent number: 10404290
    Abstract: A method and data storage system receives a confidence vector for a non-binary symbol value read from a memory cell of a non-volatile memory device, where the confidence vector includes a first plurality of confidence values and transforms the first plurality of confidence values into a first plurality of likelihood values using a forward tensor-product transform. A respective binary message passing decoding operation is performed with each of the first plurality of likelihood values to generate a second plurality of likelihood values, and the second plurality of likelihood values are transformed into a second plurality of confidence values of the confidence vector using a reverse tensor-product transform.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 3, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard Leo Galbraith, Niranjay Ravindran, Roger William Wood
  • Publication number: 20190250987
    Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A reliability metric for each symbol of each of a plurality of codewords read from the NVSM is generated, and a number of erasures for a first codeword are generated, wherein the number of erasures exceeds the correction power of the first codeword. A reliability metric of the first codeword is modified corresponding to one of the erasures. The reliability metrics for each codeword including the modified reliability metrics of the first codeword are first iteratively processed using a low density parity check (LDPC) type decoder, thereby first updating the reliability metric for each symbol of each codeword. The reliability metrics for the first codeword are second updated using the parity sector, and the second updated reliability metrics for the first codeword are second iteratively processed using the LDPC-type decoder.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 15, 2019
    Inventors: IOURI OBOUKHOV, WELDON M. HANSON, NIRANJAY RAVINDRAN, RICHARD L. GALBRAITH
  • Publication number: 20190214101
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
  • Patent number: 10236070
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 19, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
  • Publication number: 20180374550
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Application
    Filed: July 31, 2017
    Publication date: December 27, 2018
    Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
  • Publication number: 20180034479
    Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.
    Type: Application
    Filed: July 27, 2017
    Publication date: February 1, 2018
    Inventors: Richard Leo GALBRAITH, Jonas Andrew Goode, Niranjay Ravindran
  • Publication number: 20180034484
    Abstract: A method and data storage system receives a confidence vector for a non-binary symbol value read from a memory cell of a non-volatile memory device, where the confidence vector includes a first plurality of confidence values and transforms the first plurality of confidence values into a first plurality of likelihood values using a forward tensor-product transform. A respective binary message passing decoding operation is performed with each of the first plurality of likelihood values to generate a second plurality of likelihood values, and the second plurality of likelihood values are transformed into a second plurality of confidence values of the confidence vector using a reverse tensor-product transform.
    Type: Application
    Filed: July 31, 2017
    Publication date: February 1, 2018
    Inventors: Richard Leo GALBRAITH, Niranjay RAVINDRAN, Roger William WOOD