Patents by Inventor Nisha Ananthakrishnan

Nisha Ananthakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021493
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20240014097
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Patent number: 11804470
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Xavier F. Brun, Kaizad Mistry, Paul R. Start, Nisha Ananthakrishnan, Yawei Liang, Jigneshkumar P. Patel, Sairam Agraharam, Liwei Wang
  • Patent number: 11776821
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
  • Publication number: 20220165585
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.
    Type: Application
    Filed: February 10, 2022
    Publication date: May 26, 2022
    Inventors: Ziyin LIN, Vipul MEHTA, Edvin CETEGEN, Yuying WEI, Sushrutha GUJJULA, Nisha ANANTHAKRISHNAN, Shan ZHONG
  • Patent number: 11282717
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
  • Publication number: 20210242102
    Abstract: Embodiments herein describe techniques for an IC package including an electronic component, and an underfill material around or below the electronic component to support the electronic component. The underfill material includes a resin and a thermolatent onium salt as a cationic cure for the underfill material. The thermolatent onium salt comprises an organic cation with a heteroatom center, and an anion including metalloid fluoride. The heteroatom center includes an iodonium, sulphonium, phosphonium, or N-containing onium. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Elizabeth NOFEN, Ziyin LIN, Nisha ANANTHAKRISHNAN
  • Publication number: 20210066155
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20210057381
    Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Xavier F. BRUN, Kaizad MISTRY, Paul R. START, Nisha ANANTHAKRISHNAN, Yawei LIANG, Jigneshkumar P. PATEL, Sairam AGRAHARAM, Liwei WANG
  • Publication number: 20200126887
    Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled with contacts on a surface of the package substrate, underfill between the integrated circuit device and the surface of the package substrate, thermal interface material on a surface of the integrated circuit device opposite the package substrate, a heat spreader in contact with the thermal interface material, and a material on a fillet of the underfill, the material adjacent to the thermal interface material. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 23, 2020
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Jingyi Huang, Peng Li, Marco Aurelio Cartas, Nisha Ananthakrishnan
  • Patent number: 10475715
    Abstract: Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Venmathy McMahan, Sivakumar Nagarajan, Elah Bozorg-Grayeli, Amrita Mallik, Kuang-Han Chu, Liwei Wang, Nisha Ananthakrishnan, Craig J. Weinman, Amram Eitan
  • Publication number: 20190304808
    Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Ziyin LIN, Vipul MEHTA, Edvin CETEGEN, Yuying WEI, Sushrutha GUJJULA, Nisha ANANTHAKRISHNAN, Shan ZHONG
  • Publication number: 20190099776
    Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature. The includes compressible reticulated media including an input interface configured for coupling with a fluid reservoir, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the applicator profile. The compressible reticulated media includes filling and dispensing configurations. In the dispensing configuration the substrate interface is configured for engagement with the at least one substrate feature, the compressible reticulated media is compressed, and according to the compression the fluid is applied across the feature profile. In the filling configuration the compressible reticulated media is configured for expansion relative to the dispensing configuration, and the fluid infiltrates the reticulations according to the expansion.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ken P. Hackenberg, Nachiket R. Raravikar, James C. Matayabas, JR., Elizabeth Nofen, Nisha Ananthakrishnan, Manabu Nakagawasai, Yoshihiro Tomita
  • Publication number: 20190099777
    Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature includes a manifold plate having an inflow orifice and a manifold reservoir. A distributor plate is coupled with the manifold plate. The distributor plate includes a distributor surface extending across the manifold reservoir, and a distributor port array spread across the distributor surface and in communication with the manifold reservoir. A compressible reticulated media is configured for applying the fluid to the at least one substrate feature. The compressible reticulated media includes an input interface coupled along the distributor surface, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the substrate interface.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ken P. Hackenberg, Nachiket R. Raravikar, James C. Matayabas, JR., Elizabeth Nofen, Seth B. Reynolds, Amram Eitan, Nisha Ananthakrishnan
  • Patent number: 10115606
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
  • Publication number: 20180286704
    Abstract: A process for applying an underfill material to a die is disclosed. A wafer is diced into a plurality of dies (without having any underfill film thereon) such that the dies have exposed bumps prior to an underfill process. Thus, the dies can be tested about their bump-sides because the bumps are entirely exposed for testing. The dies are then reconstituted bump-side up on a carrier panel in an array such that the dies are separated from each other by a gap. Underfill material (e.g., epoxy flux film) is then vacuum laminated to the carrier panel and the plurality of dies to encapsulate the dies. The underfill material is then cut between adjacent dies such that a portion of the underfill material covers at least one side edge of each die. The encapsulated dies are then removed from the carrier panel, thereby being prepared for a thermal bonding process to a substrate. Associated devices are provided.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Elizabeth M. Nofen, Arjun Krishnan, James C. Matayabas, JR., Venmathy McMahan, Nisha Ananthakrishnan, Yonghao Xiu
  • Patent number: 9704767
    Abstract: Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Suriyakala Ramalingam, Yiqun Bai, Nisha Ananthakrishnan, Arjun Krishnan
  • Publication number: 20170186658
    Abstract: Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Suriyakala RAMALINGAM, Yiqun BAI, Nisha ANANTHAKRISHNAN, Arjun KRISHNAN
  • Publication number: 20170170088
    Abstract: Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.
    Type: Application
    Filed: June 17, 2015
    Publication date: June 15, 2017
    Inventors: Venmathy McMahan, Sivakumar Nagarajan, Elah Bozorg-Grayeli, Amrita Mallik, Kuang-Han Chu, Liwei Wang, Nisha Ananthakrishnan, Craig J. Weinman, Amram Eitan
  • Patent number: 9640415
    Abstract: Methods for covalently and indelibly anchoring a polyacrylate polymer using a UV-induced polymerization process in the presence of a photoinitiator to an oxide surface are disclosed herein. The methods and compositions prepared by the methods can be used as indelible marking materials for use on microelectronic packages and as solder and sealant barriers to prevent overspreading of liquids on the oxide surfaces of microelectronic packages. The polyacrylate polymers are covalently linked to the oxide surface by use during the printing and UV-curing process of an adhesion promoter having as a first domain an oxide-reactive silyl group, bonded via a linker to an acrylate-reactive group.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Randall D Lowe, Jr., Suriyakala Suriya Ramalingam, Nisha Ananthakrishnan, James C. Matayabas, Jr., Arjun Krishnan, Hitesh Arora