Patents by Inventor Nishant Sinha

Nishant Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS FOR FORMING CONDUCTIVE VIAS IN SEMICONDUCTOR DEVICE COMPONENTS
    Publication number: 20100133661
    Abstract: A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 3, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Nishant Sinha
  • Methods of forming semiconductor structures
    Patent number: 7713817
    Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: May 11, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Dinesh Chopra, Fred D. Fishburn
  • Methods Of Forming Capacitors, And Methods Of Utilizing Silicon Dioxide-Containing Masking Structures
    Publication number: 20100099232
    Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Inventors: Niraj Rana, Nishant Sinha, Prashant Raghu, Jim Hofmann, Neil Greeley
  • MICROELECTRONIC SUBSTRATE CLEANING SYSTEMS WITH POLYELECTROLYTE AND ASSOCIATED METHODS
    Publication number: 20100043824
    Abstract: Several embodiments of cleaning systems using polyelectrolyte and various associated methods for cleaning microelectronic substrates are disclosed herein. One embodiment is directed to a system that has a substrate support for holding the microelectronic substrate, a dispenser positioned above the substrate support and facing a surface of the microelectronic substrate, a reservoir in fluid communication with the dispenser via a conduit, and a washing solution contained in the reservoir. The washing solution includes a polyelectrolyte.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Joseph N. Greeley, Nishant Sinha, Lukasz Hupka, Timothy A. Quick, Prashant Raghu
  • Methods for forming conductive vias in semiconductor device components
    Patent number: 7666788
    Abstract: A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: February 23, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods
    Patent number: 7662719
    Abstract: A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Dinesh Chopra
  • POLISHING SYSTEMS AND METHODS FOR REMOVING CONDUCTIVE MATERIAL FROM MICROELECTRONIC SUBSTRATES
    Publication number: 20100025854
    Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.
    Type: Application
    Filed: August 4, 2008
    Publication date: February 4, 2010
    Applicant: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • INTERCONNECT STRUCTURES FOR INTEGRATION OF MULTI-LAYERED INTEGRATED CIRCUIT DEVICES AND METHODS FOR FORMING THE SAME
    Publication number: 20100013107
    Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.
    Type: Application
    Filed: July 16, 2008
    Publication date: January 21, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Nishant Sinha, John A. Smythe
  • Methods Of Forming A Non-Volatile Resistive Oxide Memory Cell And Methods Of Forming A Non-Volatile Resistive Oxide Memory Array
    Publication number: 20100003782
    Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Inventors: Nishant Sinha, John Smythe, Bhaskar Srinivasan, Gurtej Sandhu, Neil Greeley, Kunal Parekh
  • SYMBOLIC PROGRAM ANALYSIS USING TERM REWRITING AND GENERALIZATION
    Publication number: 20090281999
    Abstract: Systems and methods are disclosed for analyzing data-flow using program expressions or terms by extracting a control flow graph node from a work list; merging symbolic term values at join nodes; performing simplification of term values using rewriting logic; determining successors of the graph node to which data must be propagated; and updating symbolic data for elements of the successors.
    Type: Application
    Filed: December 9, 2008
    Publication date: November 12, 2009
    Applicant: NEC Laboratories America, Inc.
    Inventor: Nishant Sinha
  • Compositions of Matter, and Methods of Removing Silicon Dioxide
    Publication number: 20090275208
    Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.
    Type: Application
    Filed: May 2, 2008
    Publication date: November 5, 2009
    Inventor: Nishant Sinha
  • Semiconductor device components with conductive vias and systems including the components
    Patent number: 7608904
    Abstract: A semiconductor device component includes at least one conductive via. The at least one conductive via may include a seed layer for facilitating adhesion of a conductive material within the via aperture, a barrier material and solder, or a silicon-containing filler. Systems including such semiconductor device components are also disclosed.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: October 27, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • TEMPLATES FOR IMPRINT LITHOGRAPHY AND METHODS OF FABRICATING AND USING SUCH TEMPLATES
    Publication number: 20090263729
    Abstract: A template for use in imprint lithography is disclosed. The template includes at least two ultraviolet transparent materials bonded together by an ultraviolet transparent epoxy. The ultraviolet transparent epoxy is a polymeric, spin-on epoxy or a two-part, amine-cured epoxy having a viscosity at room temperature of from about 35,000 cps to about 45,000 cps. The template has a substantially uniform index of refraction. Additionally, methods of forming and using the templates are disclosed.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 22, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Nishant Sinha
  • Methods of fabricating substrates including one or more conductive vias
    Patent number: 7603772
    Abstract: Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a portion of the at least one conductive layer and exposes another portion of the at least one conductive layer to define at least one conductive element, at least a portion of which extends over the surface of the at least one aperture.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: October 20, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Steven M. McDonald, Nishant Sinha, William M. Hiatt
  • SPIN-ON FILM PROCESSING USING ACCOUSTIC RADIATION PRESSURE
    Publication number: 20090253271
    Abstract: An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure to alter the liquid topography. Other apparatus and processes are disclosed.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 8, 2009
    Inventors: Nishant Sinha, Gurtej S. Sandhu, John Smythe
  • Methods of fabricating substrates including at least one conductive via
    Patent number: 7594322
    Abstract: A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: September 29, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Steven M. McDonald, Nishant Sinha, William M. Hiatt
  • Methods of Forming Electrically Conductive Structures
    Publication number: 20090238958
    Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Inventor: Nishant Sinha
  • Rheological fluids for particle removal
    Publication number: 20090211595
    Abstract: Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Inventor: Nishant Sinha
  • MEGASONIC CLEANING WITH CONTROLLED BOUNDARY LAYER THICKNESS AND ASSOCIATED SYSTEMS AND METHODS
    Publication number: 20090173358
    Abstract: Megasonic cleaning systems and methods of using megasonic pressure waves to impart cavitation energy proximate a surface of a microelectronic substrate are disclosed herein. In one embodiment, a megasonic cleaning system includes a process tank for containing a liquid, a support element for carrying a substrate submerged in the liquid, and first and second transducers positioned in the tank. The first transducer is further positioned and/or operated to initiate cavitation events in a bulk portion of the liquid proximate a surface of the substrate. The second transducer is further positioned and/or operated to control an interface of fluid friction between the substrate and the bulk portion of the liquid.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 9, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Methods For Treating Surfaces
    Publication number: 20090114246
    Abstract: Some embodiments include methods for treating surfaces. Beads and/or other insolubles may be dispersed within a liquid carrier to form a dispersion. A transfer layer may be formed across a surface. The dispersion may be directed toward the transfer layer, and the insolubles may impact the transfer layer. The impacting may generate force in the transfer layer, and such force may be transferred through the transfer layer to the surface. The surface may be a surface of a semiconductor substrate, and the force may be utilized to sweep contaminants from the semiconductor substrate surface. The transfer layer may be a liquid, and in some embodiments may be a cleaning solution.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Inventors: Nishant Sinha, Gurtej S. Sandhu