Abstract: Systems and methods are disclosed to check properties of bounded concurrent programs by encoding concurrent control flow graph (CFG) and property for programming threads as a first-order formula F1; initializing an interference abstraction (IA); encoding the IA as a first-order formula F2; checking a conjunction of F1 and F2 (F1?F2); if the conjunction is satisfiable, checking if an interference relation (IR) is spurious, and iteratively refining the IA; and if the conjunction is unsatisfiable, checking if an interference relation (IR) is spurious, and iteratively refining the IA.

Abstract: Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memory cells at the first and second vertical levels, and a second data line over the first data line is selectively coupled to the second memory cells at the first and second vertical levels.

Abstract: Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

Abstract: Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided.

Abstract: Some embodiments include devices that contain bundles of CNTs. An undulating topography extends over the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is directly over the CNTs, with the material being a plurality of particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width. Some embodiments include methods in which a plurality of crossed carbon nanotubes are formed over a semiconductor substrate. The CNTs form an undulating upper topography extending across the CNTs and within spaces between the CNTs. A global maximum lateral width is defined as the greatest lateral width of any of the spaces. A material is deposited over the CNTs, with the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width.

Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.

Abstract: Devices with conductive through-waver vias. In one embodiment, the device is formed by a method comprising providing a layer of semiconducting material, forming a layer of metal on a first side of the layer of semiconducting material, forming an opening in the layer of semiconducting material to thereby expose a portion of the layer of metal, the opening extending from at least a second side of the layer of semiconducting material to the layer of metal, and performing a deposition process to form a conductive contact in the opening using the exposed portion of the metal layer as a seed layer.

Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

Abstract: An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with the surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.

Abstract: A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

Abstract: Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided.

Abstract: Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over the substrate layer.

Abstract: Embodiments of the invention pertain to vertical memory structures. Embodiments of the invention describe memory nodes comprising two memory cells on opposing sides of a vertical channel separating a source region and a drain region. Embodiments of the invention may utilize floating gate NAND memory cells, polysilicon diodes, MiM diodes, or MiiM diodes. Embodiments of the invention may be used to form flash memory, RRAM, Memristor RAM, Oxide Ram or OTPROM.

Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.

Abstract: Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect ratio openings may be filled with a first conductive material while the low aspect ratio openings are only partially filled with the first conductive material. Additional material may then be selectively plated over the first conductive material within the low aspect ratio openings relative to the first conductive material within the high aspect ratio openings. In some embodiments, the additional material may be activation material that only partially fills the low aspect ratio opening, and another conductive material may be subsequently plated onto the activation material to fill the low aspect ratio openings.

Abstract: A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.

Abstract: An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with the surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.