Patents by Inventor Nishant Sinha

Nishant Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865611
    Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 9, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 9865812
    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: January 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Scott E. Sills, Whitney L. West, Rob B. Goodwin, Nishant Sinha
  • Publication number: 20180004783
    Abstract: Disclosed aspects relate to database object management for a shared pool of configurable computing resources. A set of database object profile data is collected. The set of database object profile data is for a set of database objects. Based on the set of database object profile data, a set of database object priority values is determined. The set of database object priority values is for the set of database objects. Based on the set of database object priority values, a management action is performed. The management action is performed with respect to the set of database objects.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Gaurav Mehrotra, Harjindersingh G. Mistry, Pratik P. Paingankar, Nishant Sinha
  • Publication number: 20170235599
    Abstract: A computer-implemented method includes receiving, from a natural language interface system, a natural language task specification, and converting the natural language task specification into a domain independent data flow graph. The data flow graph includes substeps. The method further includes: presenting the data flow graph via the natural language interface system as a natural language program; interactively refining the natural language program; and correspondingly modifying the data flow graph. The computer-implemented method further includes, for each substep: selecting one or more candidate APIs from an API library, based on the substep; interactively narrowing the one or more candidate APIs to at least one selected API; implementing the substep by specifying one or more calls to the at least one selected API to yield a substep implementation; and appending the substep implementation to a result program. A corresponding computer program product and computer system are also disclosed.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 17, 2017
    Inventors: Dinesh Raghu, Nishant Sinha
  • Publication number: 20170220431
    Abstract: As disclosed herein a computer-implemented method for managing an HA cluster includes activating, by a cluster manager, a monitoring process that monitors a database on a first node in a high-availability database cluster. The method further includes receiving an indication that the database on the first node is not healthy, initiating a failover operation for deactivating the database on the first node and activating a standby database on a second node in the high-availability database cluster providing an activated standby database, and ensuring that any additional databases on the first node are unaffected by the failover operation. A computer program product corresponding to the above method is also disclosed.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 3, 2017
    Inventors: Juilee A. Joshi, Gaurav Mehrotra, Nishant Sinha, Jing Jing Xiao
  • Publication number: 20170220430
    Abstract: As disclosed herein a computer-implemented method for managing an HA cluster includes activating, by a cluster manager, a monitoring process that monitors a database on a first node in a high-availability database cluster. The method further includes receiving an indication that the database on the first node is not healthy, initiating a failover operation for deactivating the database on the first node and activating a standby database on a second node in the high-availability database cluster providing an activated standby database, and ensuring that any additional databases on the first node are unaffected by the failover operation. A computer program product corresponding to the above method is also disclosed.
    Type: Application
    Filed: January 18, 2017
    Publication date: August 3, 2017
    Inventors: Juilee A. Joshi, Gaurav Mehrotra, Nishant Sinha, Jing Jing Xiao
  • Patent number: 9666801
    Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: May 30, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, John Smythe, Bhaskar Srinivasan, Gurtej S. Sandhu, Joseph Neil Greeley, Kunal R. Parekh
  • Publication number: 20170092855
    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Inventors: Sanh D. Tang, Scott E. Sills, Whitney L. West, Rob B. Goodwin, Nishant Sinha
  • Patent number: 9576904
    Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: February 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Nishant Sinha, John A. Smythe
  • Publication number: 20170024446
    Abstract: An extract, transform and load (ETL) data storage system performs extract, transform and load operations to load target tables with data extracted and transformed data from multiple data sources. Transformations include matching and linking date temporarily stored in intermediate tables by entity across data sources. Data may be organized by entity and time, and analytical records can be generated from the intermediate tables according to variable transforms. The analytical records may be used for predictive analytics.
    Type: Application
    Filed: September 1, 2015
    Publication date: January 26, 2017
    Applicant: ACCENTURE GLOBAL SERVICES LIMITED
    Inventors: Matthew O'KANE, Nishant Sinha
  • Patent number: 9520558
    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: December 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Scott E. Sills, Whitney L. West, Rob B. Goodwin, Nishant Sinha
  • Publication number: 20160260899
    Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Applicant: Micron Technology, Inc.
    Inventors: Nishant Sinha, John Smythe, Bhaskar Srinivasan, Gurtej S. Sandhu, Joseph Neil Greeley, Kunal R. Parekh
  • Patent number: 9431493
    Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 30, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Publication number: 20160203062
    Abstract: Embodiments of the present invention provide methods, systems, and computer program products for prioritizing database failover. In one embodiment, an order in which to failover databases is determined based on a priority order of databases and the time at which the failover process occurs, which can be used to help reduce possible down time users can experience while waiting for the database most important to them to be failed over.
    Type: Application
    Filed: October 12, 2015
    Publication date: July 14, 2016
    Inventors: Juilee S. Hapse, Priyanka K. Joshi, Nishant Sinha
  • Publication number: 20160203051
    Abstract: Embodiments of the present invention provide methods, systems, and computer program products for prioritizing database failover. In one embodiment, an order in which to failover databases is determined based on a priority order of databases and the time at which the failover process occurs, which can be used to help reduce possible down time users can experience while waiting for the database most important to them to be failed over.
    Type: Application
    Filed: January 9, 2015
    Publication date: July 14, 2016
    Inventors: Juilee S. Hapse, Priyanka K. Joshi, Nishant Sinha
  • Patent number: 9343665
    Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, John Smythe, Bhaskar Srinivasan, Gurtej S. Sandhu, Joseph Neil Greeley, Kunal R. Parekh
  • Patent number: 9312266
    Abstract: Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: April 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John Zahurak, Siddartha Kondoju, Haitao Liu, Nishant Sinha
  • Patent number: 9287207
    Abstract: A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 9269586
    Abstract: Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: February 23, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. Morgan, Nishant Sinha
  • Publication number: 20160027883
    Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Applicant: Micron Technology, Inc.
    Inventor: Nishant Sinha