Abstract: Techniques, an apparatus and computer program product for generating test cases for covering enterprise rules and predicates are disclosed by receiving data associated with at least one of a business requirement and a business scenario as input, wherein the data comprise at least one of a set of predefined rules; based on the data, generating at least one or more test cases as output without any human intervention, wherein the output comprises a test script for the business requirement or the business scenario, and wherein the data associated with the at least one of a business requirement and a business scenario comprise at least one of a business rule, business requirement and predicate, the data associated with the at least one of business requirement and business scenario are stored as a linked graph in a repository, and wherein each node of the linked graph is mapped to previously stored data in the repository, wherein the repository comprises either one of a structured or unstructured data, and the data

Abstract: Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses of a film or other structure at undesirably high rates are also disclosed.

Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.

Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

Abstract: A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.

Abstract: Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from a surface of the substrate are provided.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

Abstract: Techniques, an apparatus and an article of manufacture for generating test cases for covering enterprise rules and predicates. A method includes obtaining a web application and a specification of at least one enterprise rule, constructing a link graph that captures at least one navigation path in the web application, and performing a traversal of the web application guided by the link graph to generate an executable test case that drives the web application along one of the at least one navigation paths in which the at least one enterprise rule is covered to determine the web application's conformance to the at least one enterprise rule, wherein the executable test case is a sequence of one or more test steps, each test step representing an action to be performed on the web application and/or a verification of the application state.

Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.

Abstract: Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from a surface of the substrate are provided.

Abstract: An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with a surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to a dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract: Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

Abstract: Systems and methods are disclosed to check properties of bounded concurrent programs by encoding concurrent control flow graph (CFG) and property for programming threads as a first-order formula F1; initializing an interference abstraction (IA); encoding the IA as a first-order formula F2; checking a conjunction of F1 and F2 (F1^F2); if the conjunction is satisfiable, checking if an interference relation (IR) is spurious, and iteratively refining the IA; and if the conjunction is unsatisfiable, checking if an interference relation (IR) is spurious, and iteratively refining the IA.

Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Abstract: Methods and systems for concurrent program verification. A concurrent program is summarized into a symbolic interference skeleton (IS) using data flow analysis. Sequential consistency constraints are enforced on read and write events in the IS. Error conditions are checked together with the IS using a processor.

Abstract: Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods.

Abstract: A system and method for analyzing a concurrent program employ asynchronous function calls for communication and recursion. A control flow graph is constructed based on a context-sensitive pointer analysis, whereupon encountering a function pointer, a points-to set of the function pointer is computed in a context-sensitive fashion to determine a set of potential function calls. The context-sensitive pointer analysis is terminated when no new potential function calls are encountered and where the potential function calls may contribute new data races other than those that exist in the contexts traversed thus far. To decide this, a characterization of pointer aliasing based upon complete update sequences is employed. A set of contexts that may contribute to different data races are enumerated by tracking update sequences for function and lock pointers and pointers that are shared or point to shared memory locations. Data race detection is carried out on the control flow graph.