Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.

Abstract: Methods for preventing isotropic removal of materials at corners faulted by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses of a film or other structure at undesirably high rates are also disclosed.

Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.

Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.

Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

Abstract: Megasonic cleaning systems and methods of using megasonic pressure waves to impart cavitation energy proximate a surface of a microelectronic substrate are disclosed herein. In one embodiment, a megasonic cleaning system includes a process tank for containing a liquid, a support element for carrying a substrate submerged in the liquid, and first and second transducers positioned in the tank. The first transducer is further positioned and/or operated to initiate cavitation events in a bulk portion of the liquid proximate a surface of the substrate. The second transducer is further positioned and/or operated to control an interface of fluid friction between the substrate and the bulk portion of the liquid.

Abstract: Techniques, an apparatus and an article of manufacture for generating test cases for covering enterprise rules and predicates. A method includes obtaining a web application and a specification of at least one enterprise rule, constructing a link graph that captures at least one navigation path in the web application, and performing a traversal of the web application guided by the link graph to generate an executable test case that drives the web application along one of the at least one navigation paths in which the at least one enterprise rule is covered to determine the web application's conformance to the at least one enterprise rule, wherein the executable test case is a sequence of one or more test steps, each test step representing an action to be performed on the web application and/or a verification of the application state.

Abstract: Methods and apparatus are provided for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing a composition of magnetic particles dispersed within a base fluid to remove contaminants from a surface of the substrate.

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Abstract: Methods and apparatus are provided for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing a composition of magnetic particles dispersed within a base fluid to remove contaminants from a surface of the substrate.

Abstract: Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.

Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

Abstract: Methods for preventing isotropic removal of materials at corners faulted by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses of a film or other structure at undesirably high rates are also disclosed.

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.