Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (IC) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

Abstract: An integrated circuit (IC) device comprises a host component and an IC die directly bonded to the host component. The IC die comprises a substrate material layer and a die metallization level between the substrate material layer and host component. The IC die includes an upper die alignment fiducial between the die metallization level and host component. The upper die alignment fiducial at least partially overlaps one or more metallization features within the die metallization level. In embodiments, at least two orthogonal edges of the upper die alignment fiducial do not overlap any of the metallization features within the die metallization level. In embodiments, the IC die includes a lower die alignment fiducial between the substrate material layer and the die metallization level. The lower die alignment fiducial may at least partially overlap one or more second metallization features within a second die metallization level of the IC die.

Abstract: Embodiments of a microelectronic assembly comprise: a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die, and a second plurality of IC dies coupled to at least the first IC die or the second IC die. Each IC die in the first plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective first planar interface, each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface, each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and the first planar interface is orthogonal to the second planar interface.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.

Abstract: Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

Abstract: Disclosed herein are microelectronic structures including bridges, and related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate with first and second metal layers; a cavity in the substrate, where a portion of the first and second metal layers, are exposed with the portion of the first metal layer partially overlapping the portion of the second metal layer; and a bridge component in the cavity, having a first conductive contact at a first face and a second conductive contact at a second face opposing the first face, the second face towards a bottom surface of the cavity, the portion of the first metal layer is between the second face of the bridge component and the portion of the second metal layer, and the second conductive contact is electrically coupled to the portion of the second metal layer in the cavity.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

Abstract: An integrated circuit assembly may be formed having a first level structure that comprises a monolithic substrate with a first reticle zone including integrated circuitry and a second reticle zone including integrated circuitry, and a second level structure comprising at least one integrated circuit device electrically attached to the integrated circuitry of the first reticle zone of the first level structure and a bridge electrically attaching the integrated circuitry of the first reticle zone of the first level structure and the integrated circuitry of the second reticle zone of the first level structure.

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate including a first metal layer and a second metal layer; a cavity in the substrate, wherein a portion of the first metal layer in the substrate and a portion of the second metal layer in the substrate are exposed in the cavity; and a bridge component in the cavity, the bridge component includes a first conductive contact at a first face and a second conductive contacts at an opposing second face, wherein the second face of the bridge component is between the first face of the bridge component and a bottom surface of the cavity in the substrate, and wherein the second conductive contact is electrically coupled to the portion of the first metal layer in the cavity.

Abstract: Covered cavity structure for Photonic integrated circuits (PICs) that include a micro-ring resonator (MRR) with a heater. Air cavities are etched or otherwise thinned into an overlaying oxide layer, a buried oxide layer, or an underlying silicon layer. Variations in size, shape, and location of the covered air cavity associated with an MRR provide customizable options for thermal management. A thin film across an upper surface covers the air cavity, providing a barrier to underfill in the air cavity and preventing interference of underfill with performance of silicon waveguides. When arrayed into a plurality of MRRs, the thin film can cover the plurality of MRRs.

Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a stack of layers coupled by at least fusion bonds; a package substrate coupled to a first layer in the stack of layers; one or more dies in the first layer; and one or more dies in a second layer in the stack of layers, the second layer coupled to the first layer, wherein: a copper lining is between adjacent surfaces of any two adjacent dies in at least one of the first layer and the second layer, and the copper lining contacts and substantially covers the adjacent surfaces. In various embodiments, the dies comprise dummy dies and integrated circuit (IC) dies, the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies having non-functional ICs, and the IC dies comprise semiconductor dies having functional ICs.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes one or more ribbon bond connections along with one or more wire bond connections. In one example, ribbon bond connections are shown, and are coupled to ground, and configured to provide a shielding effect to wire bond connections.